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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Recent experiences with implementing a video based six degree of freedom measurement system for airplane models in a 20 foot diameter vertical spin tunnel

A model space positioning system (MSPS), a state-of-the-art, real-time tracking system to provide the test engineer with on line model pitch and spin rate information, is described. It is noted that the six-degree-of-freedom post processor program will require additional programming effort both in the automated tracking mode for high spin rates and in accuracy to meet the measurement objectives. An independent multicamera system intended to augment the MSPS is studied using laboratory calibration methods based on photogrammetry to characterize the losses in various recording options. Data acquired to Super VHS tape encoded with Vertical Interval Time Code and transcribed to video disk are considered to be a reasonable priced choice for post editing and processing video data.

Snow, Walter L.↗
NASA NTRS1985

Grundy - Parallel processor architecture makes programming easy

The hardware, software, and firmware of the parallel processor, Grundy, are examined. The Grundy processor uses a simple processor that has a totally orthogonal three-address instruction set. The system contains a relative and indirect processing mode to support the high-level language, and uses pseudoprocessors and read-only memory. The system supports high-level language in which arbitrary degrees of algorithmic parallelism is expressed. The functions of the compiler and invocation frame are described. Grundy uses an operating system that can be accessed by an arbitrary number of processes simultaneously, and the access time grows only as the logarithm of the number of active processes. Applications for the parallel processor are discussed.

Meier, R. J., Jr.↗
NASA NTRS1980

The software system development for the TAMU real-time fan beam scatterometer data processors

A software package was designed and written to process in real-time any one quadrature channel pair of radar scatterometer signals form the NASA L- or C-Band radar scatterometer systems. The software was successfully tested in the C-Band processor breadboard hardware using recorded radar and NERDAS (NASA Earth Resources Data Annotation System) signals as the input data sources. The processor development program and the overall processor theory of operation and design are described. The real-time processor software system is documented and the results of the laboratory software tests, and recommendations for the efficient application of the data processing capabilities are presented.

Clark, B. V.↗
NASA NTRS1988

The role of specialized processors in the NAS program - Retrospective/prospective

The Numerical Aerodynamic Simulation (NAS) Program was initiated by NASA to establish a national resource for scientific research and engineering applications of computational fluid dynamics. This paper examines the changing views of the roles of general purpose and special purpose processors in this program in response to changes in technology as well as changes in perceived needs. The time period covered extends from more than 10 years ago, through the present, and concludes with some speculative concepts for the future roles of specialized processors in the advanced NAS system.

Levin, Eugene↗
NASA NTRS2006

Programs for Testing Processor-in-Memory Computing Systems

The Multithreaded Microbenchmarks for Processor-In-Memory (PIM) Compilers, Simulators, and Hardware are computer programs arranged in a series for use in testing the performances of PIM computing systems, including compilers, simulators, and hardware. The programs at the beginning of the series test basic functionality; the programs at subsequent positions in the series test increasingly complex functionality. The programs are intended to be used while designing a PIM system, and can be used to verify that compilers, simulators, and hardware work correctly. The programs can also be used to enable designers of these system components to examine tradeoffs in implementation. Finally, these programs can be run on non-PIM hardware (either single-threaded or multithreaded) using the POSIX pthreads standard to verify that the benchmarks themselves operate correctly. [POSIX (Portable Operating System Interface for UNIX) is a set of standards that define how programs and operating systems interact with each other. pthreads is a library of pre-emptive thread routines that comply with one of the POSIX standards.]

Katz, Daniel S.↗
NASA NTRS1978

Microcomputer technology applications: Charger and regulator software for a breadboard programmable power processor

Software programs are described, one which implements a voltage regulation function, and one which implements a charger function with peak-power tracking of its input. The software, written in modular fashion, is intended as a vehicle for further experimentation with the P-3 system. A control teleprinter allows an operator to make parameter modifications to the control algorithm during experiments. The programs require 3K ROM and 2K ram each. User manuals for each system are included as well as a third program for simple I/O control.

Green, D. M.↗
NASA NTRS1991

Development of visual 3D virtual environment for control software

Virtual environments for software visualization may enable complex programs to be created and maintained. A typical application might be for control of regional electric power systems. As these encompass broader computer networks than ever, construction of such systems becomes very difficult. Conventional text-oriented environments are useful in programming individual processors. However, they are obviously insufficient to program a large and complicated system, that includes large numbers of computers connected to each other; such programming is called 'programming in the large.' As a solution for this problem, the authors are developing a graphic programming environment wherein one can visualize complicated software in virtual 3D world. One of the major features of the environment is the 3D representation of concurrent process. 3D representation is used to supply both network-wide interprocess programming capability (capability for 'programming in the large') and real-time programming capability. The authors' idea is to fuse both the block diagram (which is useful to check relationship among large number of processes or processors) and the time chart (which is useful to check precise timing for synchronization) into a single 3D space. The 3D representation gives us a capability for direct and intuitive planning or understanding of complicated relationship among many concurrent processes. To realize the 3D representation, a technology to enable easy handling of virtual 3D object is a definite necessity. Using a stereo display system and a gesture input device (VPL DataGlove), our prototype of the virtual workstation has been implemented. The workstation can supply the 'sensation' of the virtual 3D space to a programmer. Software for the 3D programming environment is implemented on the workstation. According to preliminary assessments, a 50 percent reduction of programming effort is achieved by using the virtual 3D environment. The authors expect that the 3D environment has considerable potential in the field of software engineering.

Hirose, Michitaka↗
NASA NTRS1982

Baseband processor development for the Advanced Communications Satellite Program

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

Moat, D.↗
NASA NTRS1980

Orbit attitude processor. STS-1 bench program verification test plan

A plan for the static verification of the STS-1 ATT PROC ORBIT software requirements is presented. The orbit version of the SAPIENS bench program is used to generate the verification data. A brief discussion of the simulation software and flight software modules is presented along with a description of the test cases.

Mcclain, C. R.↗
NASA NTRS1980

Level B/C software ground navigation program. Delta-T processor

The Delta-T Processor (DTP) computes the instantaneous downtrack error in a specified orbiter onboard navigation state vector recovered via downlink telemetry. The downtrack error, expressed in units of time, is computed based on current incoming Earth based range and Doppler navigation tracking data and the ground selected onboard navigation state vector. The computed time difference when used to modify the timetag of the vector used for onboard navigation reduces the instantaneous downtrack error in this vector to within the threshold of the DTP, the input data, and the onboard software. This threshold is currently estimated to be approximately 2 to 4 nautical miles. The DTP is not restricted to using only onboard vectors. Any vector, either input via the manual entry device or accessible via the vector administration table, may be used. The DTP does not require that both data types be available.

Source record↗
NASA NTRS1986

Programable Pipelined-Image Processor

Computer serves as pipelined processor for imagery or other two-dimensional digital data. Processor does feature extraction, smoothing, edge detection, texture measurement, and stereoscoptic area correlation. Also plans routes for obstacle avoidance by robots and solves two-dimensional partial differential equations. Image processor consists of modular units: each includes set of computing elements of types particularly useful in pipelined-image processing. Flexible interconnection scheme used to route data to subsequent stages of pipeline.

Gennery, D. B.↗
NASA NTRS2008

Managing Complexity in Next Generation Robotic Spacecraft: From a Software Perspective

This presentation highlights the challenges in the design of software to support robotic spacecraft. Robotic spacecraft offer a higher degree of autonomy, however currently more capabilities are required, primarily in the software, while providing the same or higher degree of reliability. The complexity of designing such an autonomous system is great, particularly while attempting to address the needs for increased capabilities and high reliability without increased needs for time or money. The efforts to develop programming models for the new hardware and the integration of software architecture are highlighted.

Multi - threaded programming↗
NASA NTRS1993

Transient Finite Element Computations on a Variable Transputer System

A parallel program to analyze transient finite element problems was written and implemented on a system of transputer processors. The program uses the explicit time integration algorithm which eliminates the need for equation solving, making it more suitable for parallel computations. An interprocessor communication scheme was developed for arbitrary two dimensional grid processor configurations. Several 3-D problems were analyzed on a system with a small number of processors.

Smolinski, Patrick J.↗