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At least 55 records · Page 3

A sun acquisition sensor for spacecraft guidance and control

The combination of a strap-down analog sun acquisition sensor (AS) and an on-board digital programmable signal processor results in a versatile guidance and control system. The combination can orient the rotation axis of a spin-stabilized spacecraft to the sun no matter what the initial attitude of the spacecraft. During the sun orientation process, spacecraft spin rate can be sensed and supplied as an input to the control algorithm. If needed, the AS-signal processor combination can be used to perform a rhumb-line turn maneuver. In case of unexpected spacecraft operating conditions, or unplanned pointing directions, the signal processor program can be updated via earth-based transmission of another program to cover the new situation. Using only three radiation-hard cadmium-sulfide detectors, containing no moving parts, needing only a few microwatts of power, included in a volume of 550 cubic cm (a redundant pair), and weighing only 540 grams, the AS is a small, simple, sturdy sensing device.

Birnbaum, M. M.↗

Efficient matrix partitioning for optical computing

Techniques for partitioning optical linear algebra problems to make them amenable to solution using optical processors programmed with simple algorithms are explored. Generalized methods for splitting a linear algebra matrix into a series of submatrices are reviewed, showing that simple forms can be pipelined smoothly and that parallel accumulation can be achieved by beam combining on detectors or by summing electronically. The techniques offer simplified bookkeeping, algorithmic independence, and high efficiency. The computational speed will depend on the number of multiplier-accumulators devoted to the task.

Caulfield, H. J.↗

Recent experiences with implementing a video based six degree of freedom measurement system for airplane models in a 20 foot diameter vertical spin tunnel

A model space positioning system (MSPS), a state-of-the-art, real-time tracking system to provide the test engineer with on line model pitch and spin rate information, is described. It is noted that the six-degree-of-freedom post processor program will require additional programming effort both in the automated tracking mode for high spin rates and in accuracy to meet the measurement objectives. An independent multicamera system intended to augment the MSPS is studied using laboratory calibration methods based on photogrammetry to characterize the losses in various recording options. Data acquired to Super VHS tape encoded with Vertical Interval Time Code and transcribed to video disk are considered to be a reasonable priced choice for post editing and processing video data.

Snow, Walter L.↗

Systems, methods, and media for high dynamic range imaging using single-photon and conventional image sensor data

In accordance with some embodiments, systems, methods, and media for high dynamic range imaging using single-photon and conventional image sensor data are provided. In some embodiments, the system comprises: first detectors configured to detect a level of photons proportional to incident photon flux; second detectors configured to detect arrival of individual photons; a processor programmed to: receive, from the first detectors, first values indicative of photon flux from a scene with a first resolution; receive, from the second detectors, second values indicative of photon flux from the scene with a lower resolution; provide a first encoder of a trained machine learning model first flux values based on the first values, provide the second encoder of the model second flux values; receive, as output, values indicative of photon flux from the scene; and generate a high dynamic range image based on the third plurality of values.

Gutierrez Barragan, Felipe↗

Grundy - Parallel processor architecture makes programming easy

The hardware, software, and firmware of the parallel processor, Grundy, are examined. The Grundy processor uses a simple processor that has a totally orthogonal three-address instruction set. The system contains a relative and indirect processing mode to support the high-level language, and uses pseudoprocessors and read-only memory. The system supports high-level language in which arbitrary degrees of algorithmic parallelism is expressed. The functions of the compiler and invocation frame are described. Grundy uses an operating system that can be accessed by an arbitrary number of processes simultaneously, and the access time grows only as the logarithm of the number of active processes. Applications for the parallel processor are discussed.

Meier, R. J., Jr.↗

The software system development for the TAMU real-time fan beam scatterometer data processors

A software package was designed and written to process in real-time any one quadrature channel pair of radar scatterometer signals form the NASA L- or C-Band radar scatterometer systems. The software was successfully tested in the C-Band processor breadboard hardware using recorded radar and NERDAS (NASA Earth Resources Data Annotation System) signals as the input data sources. The processor development program and the overall processor theory of operation and design are described. The real-time processor software system is documented and the results of the laboratory software tests, and recommendations for the efficient application of the data processing capabilities are presented.

Clark, B. V.↗

The role of specialized processors in the NAS program - Retrospective/prospective

The Numerical Aerodynamic Simulation (NAS) Program was initiated by NASA to establish a national resource for scientific research and engineering applications of computational fluid dynamics. This paper examines the changing views of the roles of general purpose and special purpose processors in this program in response to changes in technology as well as changes in perceived needs. The time period covered extends from more than 10 years ago, through the present, and concludes with some speculative concepts for the future roles of specialized processors in the advanced NAS system.

Levin, Eugene↗

Programs for Testing Processor-in-Memory Computing Systems

The Multithreaded Microbenchmarks for Processor-In-Memory (PIM) Compilers, Simulators, and Hardware are computer programs arranged in a series for use in testing the performances of PIM computing systems, including compilers, simulators, and hardware. The programs at the beginning of the series test basic functionality; the programs at subsequent positions in the series test increasingly complex functionality. The programs are intended to be used while designing a PIM system, and can be used to verify that compilers, simulators, and hardware work correctly. The programs can also be used to enable designers of these system components to examine tradeoffs in implementation. Finally, these programs can be run on non-PIM hardware (either single-threaded or multithreaded) using the POSIX pthreads standard to verify that the benchmarks themselves operate correctly. [POSIX (Portable Operating System Interface for UNIX) is a set of standards that define how programs and operating systems interact with each other. pthreads is a library of pre-emptive thread routines that comply with one of the POSIX standards.]

Katz, Daniel S.↗

Microcomputer technology applications: Charger and regulator software for a breadboard programmable power processor

Software programs are described, one which implements a voltage regulation function, and one which implements a charger function with peak-power tracking of its input. The software, written in modular fashion, is intended as a vehicle for further experimentation with the P-3 system. A control teleprinter allows an operator to make parameter modifications to the control algorithm during experiments. The programs require 3K ROM and 2K ram each. User manuals for each system are included as well as a third program for simple I/O control.

Green, D. M.↗

Development of visual 3D virtual environment for control software

Virtual environments for software visualization may enable complex programs to be created and maintained. A typical application might be for control of regional electric power systems. As these encompass broader computer networks than ever, construction of such systems becomes very difficult. Conventional text-oriented environments are useful in programming individual processors. However, they are obviously insufficient to program a large and complicated system, that includes large numbers of computers connected to each other; such programming is called 'programming in the large.' As a solution for this problem, the authors are developing a graphic programming environment wherein one can visualize complicated software in virtual 3D world. One of the major features of the environment is the 3D representation of concurrent process. 3D representation is used to supply both network-wide interprocess programming capability (capability for 'programming in the large') and real-time programming capability. The authors' idea is to fuse both the block diagram (which is useful to check relationship among large number of processes or processors) and the time chart (which is useful to check precise timing for synchronization) into a single 3D space. The 3D representation gives us a capability for direct and intuitive planning or understanding of complicated relationship among many concurrent processes. To realize the 3D representation, a technology to enable easy handling of virtual 3D object is a definite necessity. Using a stereo display system and a gesture input device (VPL DataGlove), our prototype of the virtual workstation has been implemented. The workstation can supply the 'sensation' of the virtual 3D space to a programmer. Software for the 3D programming environment is implemented on the workstation. According to preliminary assessments, a 50 percent reduction of programming effort is achieved by using the virtual 3D environment. The authors expect that the 3D environment has considerable potential in the field of software engineering.

Hirose, Michitaka↗

Baseband processor development for the Advanced Communications Satellite Program

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

Moat, D.↗

Orbit attitude processor. STS-1 bench program verification test plan

A plan for the static verification of the STS-1 ATT PROC ORBIT software requirements is presented. The orbit version of the SAPIENS bench program is used to generate the verification data. A brief discussion of the simulation software and flight software modules is presented along with a description of the test cases.

Mcclain, C. R.↗

Level B/C software ground navigation program. Delta-T processor

The Delta-T Processor (DTP) computes the instantaneous downtrack error in a specified orbiter onboard navigation state vector recovered via downlink telemetry. The downtrack error, expressed in units of time, is computed based on current incoming Earth based range and Doppler navigation tracking data and the ground selected onboard navigation state vector. The computed time difference when used to modify the timetag of the vector used for onboard navigation reduces the instantaneous downtrack error in this vector to within the threshold of the DTP, the input data, and the onboard software. This threshold is currently estimated to be approximately 2 to 4 nautical miles. The DTP is not restricted to using only onboard vectors. Any vector, either input via the manual entry device or accessible via the vector administration table, may be used. The DTP does not require that both data types be available.

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