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At least 55 records · Page 3

Controlling prediction functional blocks used by a branch predictor in a processor

An electronic device includes a processor, a branch predictor in the processor, and a predictor controller in the processor. The branch predictor includes multiple prediction functional blocks, each prediction functional block configured for generating predictions for control transfer instructions (CTIs) in program code based on respective prediction information, the branch predictor configured to select, from among predictions generated by the prediction functional blocks for each CTI, a selected prediction to be used for that CTI. The predictor controller keeps a record of prediction functional blocks from which the branch predictor previously selected predictions for CTIs. The predictor controller uses information from the record for controlling which prediction functional blocks are used by the branch predictor for generating predictions for CTIs.

97 MATHEMATICS AND COMPUTING↗

Panel Session 57: Nuclear Power Plant Waste Management - LLW Processor Issues

This panel resulted in senior utility managers discussing issues with commercial LLW processors. LLW processors updated utilities/NPPs on new or different services or technologies being offered to assist in their radioactive waste management goals, changes to their facility license, revisions to their acceptance guidelines, and emerging compliance issues. Presentations proposed include: 1 - EnergySolutions Waste Processing Overview (Joe Heckman, EnergySolutions (USA)); 2 - Perma-Fix: A Nuclear Services and Waste Management Company (John Kelly, Perma-Fix Environmental Services (USA)); 3 - UniTech - 'Expanding to Reduce Costs' LLW Processor Update (Gregg Johnstone, UniTech Services Group, Inc. (USA)); 4 - Low - Level Radioactive Materials Processing (Michael Miller, Veolia Nuclear Solutions (USA))

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗

Architectural scaling tradeoffs in modular 3D bosonic quantum processors

We propose a modular three-dimensional bosonic quantum processor built from repeatable coupled-cavity modules linked by configurable interconnect networks. Using hardware-motivated graph-theoretic measures, we compare nearest-neighbor, hub-based, and hybrid architectures in terms of interconnect count, communication distance, resource concentration, and implementation complexity. Rather than identifying a universally optimal topology, our analysis shows how these architectures redistribute the costs of scaling, including wiring and port requirements, nonlocal communication distance, exposure to shared resources, routing bottlenecks, and scheduling overhead. Case studies of a \(3\times3\) processor and a larger hierarchical architecture further distinguish finite-size performance from asymptotic scaling. The resulting framework provides a systematic basis for evaluating modular three-dimensional bosonic processors and for identifying the device-level parameters required for quantitative hardware design.

Zhu, Shaojiang [Fermilab] (ORCID:0000000293180092)↗

Modeling information flow in a computer processor with a multi-stage queuing model

In this paper, we introduce a nonlinear stochastic model to describe the propagation of information inside a computer processor. In this model, a computational task is divided into stages, and information can flow from one stage to another. The model is formulated as a spatially-extended, continuous-time Markov chain where space represents different stages. This model is equivalent to a spatially-extended version of the M/M/s queue. The main modeling feature is the throttling function which describes the processor slowdown when the amount of information falls below a certain threshold. We derive the stationary distribution for this stochastic model and develop a closure for a deterministic ODE system that approximates the evolution of the mean and variance of the stochastic model. In conclusion, we demonstrate the validity of the closure with numerical simulations.

97 MATHEMATICS AND COMPUTING↗

Broadband unidirectional visible imaging using wafer-scale nano-fabrication of multi-layer diffractive optical processors

We present a broadband and polarization-insensitive unidirectional imager that operates at the visible part of the spectrum, where image formation occurs in one direction, while in the opposite direction, it is blocked. This approach is enabled by deep learning-driven diffractive optical design with wafer-scale nano-fabrication using high-purity fused silica to ensure optical transparency and thermal stability. Our design achieves unidirectional imaging across three visible wavelengths (covering red, green, and blue parts of the spectrum), and we experimentally validated this broadband unidirectional imager by creating high-fidelity images in the forward direction and generating weak, distorted output patterns in the backward direction, in alignment with our numerical simulations. This work demonstrates wafer-scale production of diffractive optical processors, featuring 16 levels of nanoscale phase features distributed across two axially aligned diffractive layers for visible unidirectional imaging. This approach facilitates mass-scale production of ~0.5 billion nanoscale phase features per wafer, supporting high-throughput manufacturing of hundreds to thousands of multi-layer diffractive processors suitable for large apertures and parallel processing of multiple tasks. Beyond broadband unidirectional imaging in the visible spectrum, this study establishes a pathway for artificial-intelligence-enabled diffractive optics with versatile applications, signaling a new era in optical device functionality with industrial-level, massively scalable fabrication.

36 MATERIALS SCIENCE↗

Scaling molecular dynamics beyond 100,000 processor cores for large-scale biophysical simulations

The growing interest in the complexity of biological interactions is continuously driving the need to increase system size in biophysical simulations, requiring not only powerful and advanced hardware but adaptable software that can accommodate a large number of atoms interacting through complex force fields. To address this, we developed and implemented strategies in the GENESIS molecular dynamics package designed for large numbers of processors. Long–range electrostatic interactions were parallelized by minimizing the number of processes involved in communication. Here, a novel algorithm was implemented for nonbonded interactions to increase single instruction multiple data (SIMD) performance, reducing memory usage for ultra large systems. Memory usage for neighbor searches in real–space nonbonded interactions was reduced by approximately 80%, leading to significant speedup. Using experimental data describing physical 3D chromatin interactions, we constructed the first atomistic model of an entire gene locus (GATA4). Taken together, these developments enabled the first billion–atom simulation of an intact biomolecular complex, achieving scaling to 65,000 processes (130,000 processor cores) with 1 ns/day performance.

3D modeling↗

Performance optimization, modeling and analysis of sparse matrix-matrix products on multi-core and many-core processors

Sparse matrix-matrix multiplication (SpGEMM) is a computational primitive that is widely used in areas ranging from traditional numerical applications to recent big data analysis and machine learning. Although many SpGEMM algorithms have been proposed, hardware specific optimizations for multi- and many-core processors are lacking and a detailed analysis of their performance under various use cases and matrices is not available. In this work, we firstly identify and mitigate multiple bottlenecks with memory management and thread scheduling on Intel Xeon Phi (Knights Landing or KNL). Specifically targeting many-core processors, we develop a hash-table-based algorithm and optimize a heap-based shared-memory SpGEMM algorithm. We examine their performance together with other publicly available codes. Different from the literature, our evaluation also includes use cases that are representative of real graph algorithms, such as multi-source breadth-first search or triangle counting. Our hash-table and heap-based algorithms are showing significant speedups from libraries in the majority of the cases while different algorithms dominate the other scenarios with different matrix size, sparsity, compression factor and operation type. We wrap up in-depth evaluation results and make a recipe to give the best SpGEMM algorithm for target scenario. We build the performance model for hash-table and heap-based algorithms, which supports the recipe. A critical finding is that hash-table-based SpGEMM gets a significant performance boost if the nonzeros are not required to be sorted within each row of the output matrix. Finally, we integrate our implementations into a large-scale protein clustering code named HipMCL, accelerating its SpGEMM kernel by up to 10X and achieving an overall performance boost for the whole HipMCL application by 2.6X.

97 MATHEMATICS AND COMPUTING↗

A programmable two-qubit quantum processor in silicon

Now that it is possible to achieve measurement and control fidelities for individual quantum bits (qubits) above the threshold for fault tolerance, attention is moving towards the difficult task of scaling up the number of physical qubits to the large numbers that are needed for fault-tolerant quantum computing (1,2). In this context, quantum-dot-based spin qubits could have substantial advantages over other types of qubit owing to their potential for all-electrical operation and ability to be integrated at high density onto an industrial platform (3,4,5). Initialization, readout and single- and two-qubit gates have been demonstrated in various quantum-dot-based qubit representations (6,7,8,9). However, as seen with small-scale demonstrations of quantum computers using other types of qubit (10,11,12,13), combining these elements leads to challenges related to qubit crosstalk, state leakage, calibration and control hardware. We overcome these challenges by using carefully designed control techniques to demonstrate a programmable two-qubit quantum processor in a silicon device that can perform the Deutsch–Josza algorithm and the Grover search algorithm—canonical examples of quantum algorithms that outperform their classical analogues. We characterize the entanglement in our processor by using quantum-state tomography of Bell states, measuring state fidelities of 85–89 per cent and concurrences of 73–82 per cent. These results pave the way for larger-scale quantum computers that use spins confined to quantum dots.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

Universal linear intensity transformations using spatially incoherent diffractive processors

Abstract Under spatially coherent light, a diffractive optical network composed of structured surfaces can be designed to perform any arbitrary complex-valued linear transformation between its input and output fields-of-view (FOVs) if the total number ( N ) of optimizable phase-only diffractive features is ≥~2 N i N o , where N i and N o refer to the number of useful pixels at the input and the output FOVs, respectively. Here we report the design of a spatially incoherent diffractive optical processor that can approximate any arbitrary linear transformation in time-averaged intensity between its input and output FOVs. Under spatially incoherent monochromatic light, the spatially varying intensity point spread function ( H ) of a diffractive network, corresponding to a given, arbitrarily-selected linear intensity transformation, can be written as H ( m , n ; m ′, n ′) = | h ( m , n ; m ′, n ′)| 2 , where h is the spatially coherent point spread function of the same diffractive network, and ( m , n ) and ( m ′, n ′) define the coordinates of the output and input FOVs, respectively. Using numerical simulations and deep learning, supervised through examples of input-output profiles, we demonstrate that a spatially incoherent diffractive network can be trained to all-optically perform any arbitrary linear intensity transformation between its input and output if N ≥ ~2 N i N o . We also report the design of spatially incoherent diffractive networks for linear processing of intensity information at multiple illumination wavelengths, operating simultaneously. Finally, we numerically demonstrate a diffractive network design that performs all-optical classification of handwritten digits under spatially incoherent illumination, achieving a test accuracy of >95%. Spatially incoherent diffractive networks will be broadly useful for designing all-optical visual processors that can work under natural light.

36 MATERIALS SCIENCE↗

All-optical image denoising using a diffractive visual processor

Abstract Image denoising, one of the essential inverse problems, targets to remove noise/artifacts from input images. In general, digital image denoising algorithms, executed on computers, present latency due to several iterations implemented in, e.g., graphics processing units (GPUs). While deep learning-enabled methods can operate non-iteratively, they also introduce latency and impose a significant computational burden, leading to increased power consumption. Here, we introduce an analog diffractive image denoiser to all-optically and non-iteratively clean various forms of noise and artifacts from input images – implemented at the speed of light propagation within a thin diffractive visual processor that axially spans <250 × λ, where λ is the wavelength of light. This all-optical image denoiser comprises passive transmissive layers optimized using deep learning to physically scatter the optical modes that represent various noise features, causing them to miss the output image Field-of-View (FoV) while retaining the object features of interest. Our results show that these diffractive denoisers can efficiently remove salt and pepper noise and image rendering-related spatial artifacts from input phase or intensity images while achieving an output power efficiency of ~30–40%. We experimentally demonstrated the effectiveness of this analog denoiser architecture using a 3D-printed diffractive visual processor operating at the terahertz spectrum. Owing to their speed, power-efficiency, and minimal computational overhead, all-optical diffractive denoisers can be transformative for various image display and projection systems, including, e.g., holographic displays.

36 MATERIALS SCIENCE↗

Realization of fermionic Laughlin state on a quantum processor

Strongly correlated topological phases of matter are central to modern condensed matter physics and quantum information technology but often challenging to probe and control in material systems. The experimental difficulty of accessing these phases has motivated the use of engineered quantum platforms for simulation and manipulation of exotic topological states. Among these, the Laughlin state stands as a cornerstone for topological matter, embodying fractionalization, anyonic excitations, and incompressibility. Although its bosonic analogs have been realized on programmable quantum simulators, a genuine fermionic Laughlin state has yet to be demonstrated on a quantum processor. Here, we realize the ν = 1/3 fermionic Laughlin state on IonQ’s trapped-ion quantum computer using an efficient and scalable Hamiltonian variational ansatz with 369 two-qubit gates on a 16-qubit circuit. Employing symmetry-verification error mitigation, we extract key observables that characterize the Laughlin state, including correlation hole, bulk-edge correspondence, and topological entanglement entropy, with strong agreement to exact diagonalization benchmarks. This work demonstrates an end-to-end workflow to simulate material-intrinsic topological orders and provides a starting point to explore its dynamics and excitations on digital quantum processors.

Shen, Lingnan [Univ. of Washington, Seattle, WA (U↗

Extending the computational reach of a superconducting qutrit processor

Quantum computing with qudits is an emerging approach that exploits a larger, more connected computational space, providing advantages for many applications, including quantum simulation and quantum error correction. Nonetheless, qudits are typically afflicted by more complex errors and suffer greater noise sensitivity which renders their scaling difficult. In this work, we introduce techniques to tailor arbitrary qudit Markovian noise to stochastic Weyl–Heisenberg channels and mitigate noise that commutes with our Clifford and universal two-qudit gate in generic qudit circuits. We experimentally demonstrate these methods on a superconducting transmon qutrit processor, and benchmark their effectiveness for multipartite qutrit entanglement and random circuit sampling, obtaining up to 3× improvement in our results. To the best of our knowledge, this constitutes the first-ever error mitigation experiment performed on qutrits. Our work shows that despite the intrinsic complexity of manipulating higher-dimensional quantum systems, noise tailoring and error mitigation can significantly extend the computational reach of today’s qudit processors.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

A quantum processor based on coherent transport of entangled atom arrays

The ability to engineer parallel, programmable operations between desired qubits within a quantum processor is key for building scalable quantum information systems. In most state-of-the-art approaches, qubits interact locally, constrained by the connectivity associated with their fixed spatial layout. Here we demonstrate a quantum processor with dynamic, non-local connectivity, in which entangled qubits are coherently transported in a highly parallel manner across two spatial dimensions, between layers of single- and two-qubit operations. Our approach makes use of neutral atom arrays trapped and transported by optical tweezers; hyperfine states are used for robust quantum information storage, and excitation into Rydberg states is used for entanglement generation. We use this architecture to realize programmable generation of entangled graph states, such as cluster states and a seven-qubit Steane code state. Furthermore, we shuttle entangled ancilla arrays to realize a surface code state with thirteen data and six ancillary qubits and a toric code state on a torus with sixteen data and eight ancillary qubits. Finally, we use this architecture to realize a hybrid analogue–digital evolution and use it for measuring entanglement entropy in quantum simulations, experimentally observing non-monotonic entanglement dynamics associated with quantum many-body scars. Realizing a long-standing goal, these results provide a route towards scalable quantum processing and enable applications ranging from simulation to metrology.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Measurement-induced entanglement and teleportation on a noisy quantum processor

Measurement has a special role in quantum theory: by collapsing the wavefunction, it can enable phenomena such as teleportation and thereby alter the ‘arrow of time’ that constrains unitary evolution. When integrated in many-body dynamics, measurements can lead to emergent patterns of quantum information in space–time that go beyond the established paradigms for characterizing phases, either in or out of equilibrium. For present-day noisy intermediate-scale quantum (NISQ) processors, the experimental realization of such physics can be problematic because of hardware limitations and the stochastic nature of quantum measurement. Here we address these experimental challenges and study measurement-induced quantum information phases on up to 70 superconducting qubits. By leveraging the interchangeability of space and time, we use a duality mapping to avoid mid-circuit measurement and access different manifestations of the underlying phases, from entanglement scaling to measurement-induced teleportation. We obtain finite-sized signatures of a phase transition with a decoding protocol that correlates the experimental measurement with classical simulation data. The phases display remarkably different sensitivity to noise, and we use this disparity to turn an inherent hardware limitation into a useful diagnostic. Our work demonstrates an approach to realizing measurement-induced physics at scales that are at the limits of current NISQ processors.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Conceptual study of a two-layer silicon pixel detector to tag the passage of muons from cosmic sources through quantum processors

Abstract Recent studies in quantum computing have shown that quantum error correction with large numbers of physical qubits are limited by ionizing radiation from high-energy particles. Depending on the physical setup of the quantum processor, the contribution of muons from cosmic sources can constitute a significant fraction of these interactions. As most of these muons are difficult to stop, we perform a conceptual study of a two-layer silicon pixel detector to tag their hits on a solid-state quantum processor instead. With a typical dilution refrigerator geometry model, we find that efficiencies greater than 50% are most likely to be achieved if at least one of the layers is operated at the deep-cryogenic (<1 K) flanges of the refrigerator. Following this finding, we further propose a novel research program that could allow the development of silicon pixel detectors that are fast enough to provide input to quantum error correction algorithms, can operate at deep-cryogenic temperatures, and have very low power consumption.

Instruments & Instrumentation↗

Probing quantum processor performance with pyGSTi

PyGSTi is a Python software package for assessing and characterizing the performance of quantum computing processors. It can be used as a standalone application, or as a library, to perform a wide variety of quantum characterization, verification, and validation (QCVV) protocols on as-built quantum processors. In this work, we outline pyGSTi's structure, and what it can do, using multiple examples. We cover its main characterization protocols with end-to-end implementations. These include gate set tomography, randomized benchmarking on one or many qubits, and several specialized techniques. We also discuss and demonstrate how power users can customize pyGSTi and leverage its components to create specialized QCVV protocols and solve user-specific problems.

97 MATHEMATICS AND COMPUTING↗

Simulating noise on a quantum processor: interactions between a qubit and resonant two-level system bath

Material defects fundamentally limit the coherence times of superconducting qubits, and manufacturing completely defect-free devices is not yet possible. Therefore, understanding the interactions between defects and a qubit in a real quantum processor design is essential. We build a model that incorporates the standard tunneling model, the electric field distributions in the qubit, and open quantum system dynamics, and draws from the current understanding of two-level system (TLS) theory. Specifically, we start with one million TLSs distributed on the surface of a qubit and pick the 200 systems that are most strongly coupled to the qubit. We then perform a full Lindbladian simulation that explicitly includes the coherent coupling between the qubit and the TLS bath to model the time dependent density matrix of resonant TLS defects and the qubit. We find that the 200 most strongly coupled TLSs can accurately describe the qubit energy relaxation time. This work confirms that resonant TLSs located in areas where the electric field is strong can significantly affect the qubit relaxation time, even if they are located far from the Josephson junction (JJ). Similarly, a strongly-coupled resonant TLS located in the JJ does not guarantee a reduced qubit relaxation time if a more strongly coupled TLS is far from the JJ. In addition to the coupling strengths between TLSs and the qubit, the model predicts that the geometry of the device and the TLS relaxation time play a significant role in qubit dynamics. Our work can provide guidance for future quantum processor designs with improved qubit coherence times.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

A cryogenic muon tagging system based on kinetic inductance detectors for superconducting quantum processors

Ionizing radiation has emerged as a potential limiting factor for superconducting quantum processors, inducing quasiparticle bursts and correlated errors that challenge fault-tolerant operation. Atmospheric muons are particularly problematic due to their high energy and penetration power, making passive shielding ineffective. Therefore, monitoring the real-time muon flux is crucial to guide the development of alternative error-correction or mitigation strategies. We present the design, simulation, and first operation of a cryogenic muon-tagging system based on kinetic inductance detectors (KIDs), developed as a stand-alone cryogenic particle-tagging module for superconducting quantum processors. The system consists of two KIDs arranged in a vertical stack and operated at ∼20 mK. Monte Carlo simulations based on Geant4 guided the prototype design and provided reference expectations for muon-tagging efficiency and accidental coincidences due to ambient γ-rays. We observed a muon-induced coincidence rate among the top and bottom detectors of (192 ± 9) $\times\,10^{-3}$ events s$^{−1}$, in excellent agreement with the Monte Carlo prediction. The prototype achieves a muon-tagging efficiency of about 90% with negligible dead time. These results demonstrate the feasibility of operating a muon-tagging system at millikelvin temperatures and represent a key step toward the integration of cryogenic veto systems with multi-qubit chips to mitigate muon-induced errors.

Mariani, Ambra [INFN, Rome] (ORCID:000000028184857↗