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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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53 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2013

Silicon Heat Pipe Array

Improved methods of heat dissipation are required for modern, high-power density electronic systems. As increased functionality is progressively compacted into decreasing volumes, this need will be exacerbated. High-performance chip power is predicted to increase monotonically and rapidly with time. Systems utilizing these chips are currently reliant upon decades of old cooling technology. Heat pipes offer a solution to this problem. Heat pipes are passive, self-contained, two-phase heat dissipation devices. Heat conducted into the device through a wick structure converts the working fluid into a vapor, which then releases the heat via condensation after being transported away from the heat source. Heat pipes have high thermal conductivities, are inexpensive, and have been utilized in previous space missions. However, the cylindrical geometry of commercial heat pipes is a poor fit to the planar geometries of microelectronic assemblies, the copper that commercial heat pipes are typically constructed of is a poor CTE (coefficient of thermal expansion) match to the semiconductor die utilized in these assemblies, and the functionality and reliability of heat pipes in general is strongly dependent on the orientation of the assembly with respect to the gravity vector. What is needed is a planar, semiconductor-based heat pipe array that can be used for cooling of generic MCM (multichip module) assemblies that can also function in all orientations. Such a structure would not only have applications in the cooling of space electronics, but would have commercial applications as well (e.g. cooling of microprocessors and high-power laser diodes). This technology is an improvement over existing heat pipe designs due to the finer porosity of the wick, which enhances capillary pumping pressure, resulting in greater effective thermal conductivity and performance in any orientation with respect to the gravity vector. In addition, it is constructed of silicon, and thus is better suited for the cooling of semiconductor devices.

Yee, Karl Y.↗
NASA NTRS2018

Challenges and Opportunities in Gen3 Embedded Cooling with High-Quality Microgap Flow

Gen3, Embedded Cooling, promises to revolutionize thermal management of advanced microelectronic systems by eliminating the sequential conductive and interfacial thermal resistances which dominate the present 'remote cooling' paradigm. Single-phase interchip microfluidic flow with high thermal conductivity chips and substrates has been used successfully to cool single transistors dissipating more than 40kW/sq cm, but efficient heat removal from transistor arrays, larger chips, and chip stacks operating at these prodigious heat fluxes would require the use of high vapor fraction (quality), two-phase cooling in intra- and inter-chip microgap channels. The motivation, as well as the challenges and opportunities associated with evaporative embedded cooling in realistic form factors, is the focus of this paper. The paper will begin with a brief review of the history of thermal packaging, reflecting the 70-year 'inward migration' of cooling technology from the computer-room, to the rack, and then to the single chip and multichip module with 'remote' or attached air- and liquid-cooled coldplates. Discussion of the limitations of this approach and recent results from single-phase embedded cooling will follow. This will set the stage for discussion of the development challenges associated with application of this Gen3 thermal management paradigm to commercial semiconductor hardware, including dealing with the effects of channel length, orientation, and manifold-driven centrifugal acceleration on the governing behavior.

microchannel↗
NASA NTRS2017

High Density Packaging Technologies for RF Electronics in Small Spacecraft

This paper will describe a few high density packaging technologies which we are currently exploring for use in current and future small spacecraft applications. The three categories of technologies include organic multichip modules (MCMs), ceramic leadless surface mount technology (SMT) and 3D printed waveguide structures. There are many other packaging technologies that currently exist but these three were selected in part due to their long heritage in various commercial, military and space applications along with each having a relatively clear path to flight. For each of these technologies, detailed examples will be included in which hardware has been fabricated and tested for use in RF electronics for spacecraft transponders. The organic MCM example will be described in most detail and it utilizes a packaging technology by the name of CoreEZ which is a trademark of i3 Electronics. This MCM has shrunk a portion of our electronics down to 1/8th of its previous area. The CoreEZ technology has been shown to be rad hard beyond a total ionizing dose (TID) of 300kRad and the MCM which was fabricated has gone through thermal cycling and shown to have no degradation in performance. The ceramic leadless package examples include packages from high reliability manufactures by the name of KCB solutions and Barry Industries. In the case of KCB solutions, we have multiple products that will be described including a hermetic ceramic carrier which houses three microwave monolithic integrated circuits (MMICs) along with small discrete components. Finally, we will discuss the results of our search for a 3D printing process that allows us to reduce the cost and volume of our waveguide filters and diplexers for low cost small satellite applications. We have fabricated a few prototypes using direct metal laser sintering (DMLS) and metal coated plastics. Each of these packaging technology discussions will have a brief overview of its current and future use.

Aquirre, Fernando↗
NASA NTRS2016

High Density Packaging Technologies for RF Electronics in Small Spacecraft

This paper will describe a few high density packaging technologies which we are currently exploring for use in current and future small spacecraft applications. The three categories of technologies include organic multichip modules (MCMs), ceramic leadless surface mount technology (SMT) and 3D printed waveguide structures. There are many other packaging technologies that currently exist but these three were selected in part due to their long heritage in various commercial, military and space applications along with each having a relatively clear path to flight. For each of these technologies, detailed examples will be included in which hardware has been fabricated and tested for use in RF electronics for spacecraft transponders. The organic MCM example will be described in most detail and it utilizes a packaging technology by the name of CoreEZ which is a trademark of i3 Electronics. This MCM has shrunk a portion of our electronics down to 1/8th of its previous area. The CoreEZ technology has been shown to be rad hard beyond a total ionizing dose (TID) of 300kRad and the MCM which was fabricated has gone through thermal cycling and shown to have no degradation in performance. The ceramic leadless package examples include packages from high reliability manufactures by the name of KCB solutions and Barry Industries. In the case of KCB solutions, we have multiple products that will be described including a hermetic ceramic carrier which houses three microwave monolithic integrated circuits (MMICs) along with small discrete components. Finally, we will discuss the results of our search for a 3D printing process that allows us to reduce the cost and volume of our waveguide filters and diplexers for low cost small satellite applications. We have fabricated a few prototypes using direct metal laser sintering (DMLS) and metal coated plastics. Each of these packaging technology discussions will have a brief overview of its current and future use.

Schatzel, Donald↗
DOE OSTI2023

Electrical interconnect structure using metal bridges to interconnect die

A multichip module comprises a carrier, a plurality of chips, an electrical insulating layer, and an electrical interconnect structure. The carrier includes a bottom wall and four side walls defining an internal cavity. The chips are positioned in the internal cavity, with each chip including a plurality of bond pads. The electrical insulating layer is formed from electrically insulating material and is positioned on an upper surface of the carrier and the chips. The electrical interconnect structure includes a plurality of interconnect traces, with each interconnect trace formed from electrically conductive material and electrically connected to a first bond pad on a first chip and a second bond pad on a second chip. Each interconnect trace includes a bridge having a segment that is spaced apart from, and positioned above, the electrical insulating layer.

Young, Barbara Diane↗
DOE OSTI2021

3-D Prismatic Packaging Methodologies for Wide Band Gap Power Electronics Modules

In a power module the parasitic inductance limits the dynamic high-frequency performance, and the area of the cooling surfaces limits the power capability. This paper presents a new 3D power electronic design methodology based on the concept of mutual inductance cancellation and multi-sided heat transfer. New 3D prismatic packaging concepts are proposed for Wide Band Gap (WBG) power devices, where the devices can be mounted at acute angles to adjacent interconnects or other devices. Discussion is given on electrical and thermal path optimization in a 3D space. To validate the 3D prismatic packaging methodology, a 1200V/50A SiC half-bridge power module is fabricated and tested for electrical and thermal performance and results are compared with simulations. The power density calculated for the module is 12 kW/in3 (including heatsink) and shows a 31.3% inductance reduction compared to a 2D planar module. Finally, design guidance suggested for utilizing prismatic structures is provided, together with suggested future work in the area. This paper presents the first reported true 3D power module.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2024

Foreword: Special Section on Multiphysics Aspects of Power Electronics Packaging - Power Die, Power Module, and Converter Level - Part 1

Power electronics are increasingly being used to condition electricity for a wide array of applications, such as transportation (on land, air, and water), data centers, radio frequency, directed energy, wind, solar, and grid-tied applications. To increase power density, performance, efficiency, and reliability and reduce cost, innovations and developments are needed in the multiphysics packaging of power electronics at a die, module, and converter level. This includes fundamental research and development related to emerging high-voltage, high-temperature, and high-switching-frequency power electronics; packaging materials; thermal materials and interfaces; fluid-based thermal management technologies; reliability; condition monitoring; and prognostics. To address these important aspects, this Special Section on Multiphysics Aspects of Power Electronics Packaging includes several articles to be published in two parts. More details are given below on the articles included in the first part.

condition monitoring↗
NASA NTRS1989

Solar dynamic power module design

Studies have shown that use of solar dynamic (SD) power for the growth eras of the Space Station Freedom program will result in life cycle cost savings when compared to power supplied by photovoltaic sources. In the SD power module, a concentrator collects and focuses solar energy into a heat receiver which has integral thermal energy storage. A power conversion unit (PCU) based on the closed Brayton thermodynamic cycle removes thermal energy from the receiver and converts that energy to electrical energy. Since the closed Brayton cycle is a single phase gas cycle, the conversion hardware (heat exchangers, turbine, compressor, etc.) can be designed for operation in low earth orbit, and tested with confidence in test facilities on earth before launch into space. The concentrator subassemblies will be aligned and the receiver/PCU/radiator combination completely assembled and charged with gas and cooling liquid on earth before launch to, and assembly on orbit.

Space power↗
DOE OSTI2024

Foreword: Special Section on Multiphysics Aspects of Power Electronics Packaging—Power Die, Power Module, and Converter Level: Part 2

Power electronics are increasingly being used to condition electricity for a wide array of applications, such as transportation (on land, air, and water), data centers, radio frequency, directed energy, wind, solar, and grid-tied applications. Here, to increase power density, performance, efficiency, and reliability-as well as to reduce cost-innovations and developments are needed in the multiphysics packaging of power electronics at a die, module, and converter level. This includes fundamental R&D related to emerging high-voltage, high-temperature, and high-switching-frequency power electronics, packaging materials, thermal materials and interfaces, fluid-based thermal management technologies, reliability, condition monitoring, and prognostics. Latest developments in this area are published as a Special Section on Multiphysics Aspects of Power Electronics Packaging. The first part was published in the May 2024 issue of the IEEE Transactions on Components, Packaging and Manufacturing Technology (Volume 14, Issue 5). The second part of that Special Section is being published in this issue. A brief summary of the papers included in the second part are given below.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2023

Introduction to the Special Section on Control and Management of Electric Power Systems With High Shares of Inverter-Based Resources

The growing interest in the integration of variable renewable energy (VRE) and distributed energy resources (DER) on both policy and economic grounds is driving the transformation of electric power systems. The significant deployment of VRE and DER can effectively displace the conventional synchronous generator-based power plants that for decades have been the foundation for power system generation and stability in electric power systems. Inverter-based resources (IBRs) introduce a high-level of uncertainty, variability, and complexity into the operation of electric power networks, and the transformation to IBRs raises a wide range of technical questions and operational challenges. The optimal coordination and control of these resources requires greater interoperability and necessitates significant upgrades of grid automation, including real-time monitoring.

distributed power generation↗
DOE OSTI2020

Mathematics of Gas Ingress of Hermetic Packages

Herein, we have derived a gas ingress and egress equation from the first principles of ideal gases. This work is intended to benefit the hermetic microelectronics packaging community, but it may be applied to other fields that require a deep understanding of gas ingress and egress dynamics. The equation outlined herein encompasses package material properties, package characteristics, hermetic testing conditions, and service conditions. It serves as a practical utility for calculating package pressure changes due to gas ingress and egress and, therefore, a power tool for component and system service life predictions.

42 ENGINEERING↗
NASA NTRS1996

On-board Neural Processor Design for an Intelligent Multi-sensor Microspacecraft

A compact VLSI neural processor based on the Optimization Cellular Neural Network (OCNN)has been under development to provide a wide range of support for an intelligent remote sensing microspacecraft which requires both high bandwidth communication and high-performance computing for on-board data analysis, thematic data reduction, synergy of multiple types of sensors, and other smart-sensor functions. The OCNN architecture is a programmable multi-dimensional array of neurons which are locally connected with their local neurons. The OCNN operation theory, architecture, design and implementation, prototype chip, and system applications have been investigated in detail and presented in this paper.

array↗
NASA NTRS1994

Interpreter composition issues in the formal verification of a processor-memory module

This report describes interpreter composition techniques suitable for the formal specification and verification of a processor-memory module using the HOL theorem proving system. The processor-memory module is a multichip subsystem within a fault-tolerant embedded system under development within the Boeing Defense and Space Group. Modeling and verification methods were developed that permit provably secure composition at the transaction-level of specification, significantly reducing the complexity of the hierarchical verification of the system.

Fura, David A.↗