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Results for “minimodules”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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39 records · Page 3

All sources NASA NTRS DOE OSTI

NASA NTRS1981

High resolution, low cost solar cell contact development

The MIDFILM cell fabrication and encapsulation processes were demonstrated as a means of applying low-cost solar cell collector metallization. The average cell efficiency of 12.0 percent (AM1, 28 C) was achieved with fritted silver metallization with a demonstration run of 500 starting wafers. A 98 percent mechanical yield and 80 percent electrical yield were achieved through the MIDFILM process. High series resistance was responsible for over 90 percent of the electrical failures and was the major factor causing the low average cell efficiency. Environmental evaluations suggest that the MIDFILM cells do not degrade. A slight degradation in power was experienced in the MIDFILM minimodules when the AMP Solarlok connector delaminated during the environmental testing.

Mardesich, N.↗

NASA NTRS1981

A Module Experimental Process System Development Unit (MEPSDU)

The development of a cost effective process sequence that has the potential for the production of flat plate photovoltaic modules which meet the price goal in 1986 of 70 cents or less per Watt peak is described. The major accomplishments include (1) an improved AR coating technique; (2) the use of sand blast back clean-up to reduce clean up costs and to allow much of the Al paste to serve as a back conductor; and (3) the development of wave soldering for use with solar cells. Cells were processed to evaluate different process steps, a cell and minimodule test plan was prepared and data were collected for preliminary Samics cost analysis.

Source record↗

NASA NTRS1981

Evaluation and verification of epitaxial process sequence for silicon solar-cell production

To achieve the program goals, 28 minimodules were fabricated and tested, using 600 cells made from three-inch-diameter wafers processed by the sequence chosen for this purpose. Of these 600 cells, half were made from epitaxially grown layers on potentially low-cost substrates. The other half were made from commercial semiconductor-grade (SG), single-crystal silicon wafers that served as controls. Cell processing was normally performed on mixed lots containing significant numbers of each of these two types of wafers. After evaluation of the performance of all cells, they were separated by types for incorporation into modules that were to be tested for electrical performance and response to environmental stress. A simplified flow chart displaying this scheme, for quantities representing half of the planned total to be processed, is presented.

Redfield, D.↗