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At least 55 records · Page 3

Resistive memory for radiation resistant non-volatile memory (NSTRF Final Report)

As space programs increase in number and scope, there is an increasing need for radiation-hardened electronic devices and circuits. In particular, missions to high-radiation environments, such as Europa, would greatly benefit from improved radiation hardness in electronic devices. In pursuit of this goal, resistive memory (RRAM) devices were fabricated at SUNY Polytechnic Institute and evaluated for radiation hardness. Our objectives were to produce RRAM devices resistant to high levels of radiation damage and to demonstrate that these devices would improve mission lifetime in high-radiation environments. Furthermore, the underlying mechanisms of radiation were investigated to provide recommendations for radiation-hardening RRAM devices, which could be applied to any candidate RRAM devices being considered for space applications. Devices were fabricated using several fabrication approaches, including patterning by shadow mask, photolithography-based etching, and photolithography-based liftoff. In each of these cases, total ionizing dose (TID) effects and displacement damage dose (DDD) effects were measured. TID effects from exposure to a 60Co gamma source were not observed to cause changes in device resistance or switching parameters in any experiments, with each device tested to at least 20 Mrad(Si). DDD was measured as radiation-generated oxygen vacancies per cm 3 since oxygen vacancies are generally considered to be the active species involved in switching these devices. The lowest DDD level that caused a device to change resistance state was 10 21 vacancies per cm 3 , and most devices failed at 1022 vacancies per cm 3 . This is an extremely high DDD level, even for RRAM devices, which have been reported to fail in the range of 10 17 -10 20 vacancies per cm 3 . For comparison, an example flash memory device failed at 10 15 vacancies per cm 3 . Vendor-fabricated devices with a similar composition to our own were also tested against TID and DDD. The vendor-fabricated devices did not exhibit changes due to TID, up to the tested level of 30 Mrad(Si). Meanwhile, vendor devices exhibited resistance state changes at 10 21 vacancies per cm 3 , similar to our own devices. These results indicate that Ta0x-based RRAM devices may be particularly resilient to both TID and DDD effects. The very high tolerance to radiation effects is most likely due to the high intrinsic concentration of oxygen vacancies within our devices. Based on X-ray photoelectron spectroscopy (XPS) measurements, there are approximately 10 22 oxygen vacancies per cm 3 in our devices as deposited. Most devices failed when the radiation-induced vacancies reached this level, indicating suggesting that a high intrinsic vacancy concentration protects against lower levels of displacement damage. High vacancy concentration likely also protects against TID by facilitating leakage of trapped charge out of the oxide. The use of a thin switching oxide (25 nm Ta0 x , for our devices) is also expected to improve radiation hardness, as there is less room for charge trapping. Therefore, those wishing to produce very radiation-tolerant RRAM devices can probably achieve this by using a thin oxide that contains a high intrinsic concentration of oxygen vacancies. Our devices appear to be very tolerant of radiation effects, and would greatly increase the expected lifetime of a mission to Europa or another high-radiation target compared to flash memory devices. The similar radiation performance of vendor-fabricated devices is promising for adoption of RRAM devices as radiation-hardened memory devices for use in space. With continued commercial development of these devices, RRAM devices are strong candidates for next-generation memories that are inherently rad-hard.

36 MATERIALS SCIENCE↗

Recoverable distributed shared virtual memory - Memory coherence and storage structures

This paper examines the problem of implementing rollback recovery in multicomputer distributed shared virtual memory environments, in which the shared memory is implemented in software and exists only virtually. A user-transparent checkpointing recovery scheme and new twin-page disk storage management are presented to implement a recoverable distributed shared virtual memory. The checkpointing scheme is integrated with the shared virtual memory management. The twin-page disk approach allows incremental checkpointing without an explicit undo at the time of recovery. A single consistent checkpoint state is maintained on stable disk storage. The recoverable distributed shared virtual memory allows the system to restart computation from a previous checkpoint due to a processor failure without a global restart.

Wu, Kun-Lung↗

Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

97 MATHEMATICS AND COMPUTING↗

Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

97 MATHEMATICS AND COMPUTING↗

Memory object tagged memory monitoring method and system

Described are a method and processing apparatus to tag and track objects related to memory allocation calls. An application or software adds a tag to a memory allocation call to enable object level tracking. An entry is made into an object tracking table, which stores the tag and a variety of statistics related to the object and associated memory devices. The object statistics may be queried by the application to tune power/performance characteristics either by the application making runtime placement decisions, or by off-line code tuning based on a previous run. The application may add a tag to a memory allocation call to specify the type of memory characteristics requested based on the object statistics.

Roberts, David A.↗

Intrinsic two-way shape memory effect in a Ni-Mn-Sn metamagnetic shape memory microwire

We report an intrinsic two-way shape memory effect with a fully recoverable strain of 1.0% was achieved in an as-prepared Ni 50 Mn 37.5 Sn 12.5 metamagnetic shape memory microwire fabricated by Taylor-Ulitovsky method. This two-way shape memory effect is mainly owing to the internal stress caused by the retained martensite in austenite matrix, as revealed by transmission electron microscopy observations and high-energy X-ray diffraction experiments. After superelastic training for 30 loading/unloading cycles at room temperature, the amount of retained martensite increased and the recoverable strain of two-way shape memory effect increased significantly to 2.2%. Furthermore, a giant recoverable strain of 11.2% was attained under a bias stress of 300 MPa in the trained microwire. These properties confer this microwire great potential for micro-actuation applications.

36 MATERIALS SCIENCE↗

A programmable shared-memory system for an array of processing-in-memory devices

Processing in memory (PIM), the concept of integrating processing directly with memory has been attracting a lot of attention, since PIM can assist in overcoming the throughput limitation caused by data movement between CPU and memory. The challenge, however, is that it requires the programmers to have a deep understanding of the PIM architecture to maximize the benefits such as data locality and parallel thread execution on multiple PIM devices. In this study, we present AnalyzeThat, a programmable shared-memory system for parallel data processing with PIM devices. Thematic to AnalyzeThat is a rich PIM-aware data structure (PADS), which is an encapsulation that integrally ties together the data, the analysis tasks and the runtime needed to interface with the PIM device array. The PADS abstraction provides (i) a sophisticated key-value data container that allows programmers to easily store data on multiple PIMs, (ii) a suite of parallel operations with which users can easily implement data analysis applications, and (iii) a runtime, hidden to programmers, which provides the mechanisms needed to overlay both the data and the tasks on the PIM device array in an intelligent fashion, based on PIM-specific information collected from the hardware. We have developed a PIM emulation framework called AnalyzeThat. In conclusion, our experimental evaluation with representative data analytics applications suggests that the proposed system can significantly reduce the PIM programming effort without losing its technology benefits.

97 MATHEMATICS AND COMPUTING↗

Measuring color memory in a color glass condensate at electron–ion colliders

The color memory effect is the non-abelian gauge theory analog of the gravitational memory effect, in which the passage of color radiation induces a net relative SU(3) color rotation of a pair of nearby quarks. It is proposed that this effect can be measured in the Regge limit of deeply inelastic scattering at electron–ion colliders.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

Zinc-oxide charge trapping memory cell with ultra-thin chromium-oxide trapping layer

A functional zinc-oxide based SONOS memory cell with ultra-thin chromium oxide trapping layer was fabricated. A 5 nm CrO{sub 2} layer is deposited between Atomic Layer Deposition (ALD) steps. A threshold voltage (V{sub t}) shift of 2.6V was achieved with a 10V programming voltage. Also for a 2V V{sub t} shift, the memory with CrO{sub 2} layer has a low programming voltage of 7.2V. Moreover, the deep trapping levels in CrO{sub 2} layer allows for additional scaling of the tunnel oxide due to an increase in the retention time. In addition, the structure was simulated using Physics Based TCAD. The results of the simulation fit very well with the experimental results providing an understanding of the charge trapping and tunneling physics.

36 MATERIALS SCIENCE↗

A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems

Non-volatile memory (NVM) devices, such as Flash, phase change RAM, spin transfer torque RAM, and resistive RAM, offer several advantages and challenges when compared to conventional memory technologies, such as DRAM and magnetic hard disk drives (HDDs). Here, we present a survey of software techniques that have been proposed to exploit the advantages and mitigate the disadvantages of NVMs when used for designing memory systems, and, in particular, secondary storage (e.g., solid state drive) and main memory. Furthermore, we classify these software techniques along several dimensions to highlight their similarities and differences. Given that NVMs are growing in popularity, we believe that this survey will motivate further research in the field of software technology for NVMs.

97 MATHEMATICS AND COMPUTING↗

Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing

Operation speed is a key challenge in phase-change random-access memory (PCRAM) technology, especially for achieving subnanosecond high-speed cache memory. Commercialized PCRAM products are limited by the tens of nanoseconds writing speed, originating from the stochastic crystal nucleation during the crystallization of amorphous germanium antimony telluride (Ge 2 Sb 2 Te 5 ). Here, we demonstrate an alloying strategy to speed up the crystallization kinetics. The scandium antimony telluride (Sc 0.2 Sb 2 Te 3 ) compound that we designed allows a writing speed of only 700 picoseconds without preprogramming in a large conventional PCRAM device. This ultrafast crystallization stems from the reduced stochasticity of nucleation through geometrically matched and robust scandium telluride (ScTe) chemical bonds that stabilize crystal precursors in the amorphous state. Controlling nucleation through alloy design paves the way for the development of cache-type PCRAM technology to boost the working efficiency of computing systems.

Science & Technology - Other Topics↗

A study of the viability of exploiting memory content similarity to improve resilience to memory errors

Building the next-generation of extreme-scale distributed systems will require overcoming several challenges related to system resilience. As the number of processors in these systems grow, the failure rate increases proportionally. One of the most common sources of failure in large-scale systems is memory. In this paper, we propose a novel runtime for transparently exploiting memory content similarity to improve system resilience by reducing the rate at which memory errors lead to node failure. We evaluate the viability of this approach by examining memory snapshots collected from eight high-performance computing (HPC) applications and two important HPC operating systems. Based on the characteristics of the similarity uncovered, we conclude that our proposed approach shows promise for addressing system resilience in large-scale systems.

97 MATHEMATICS AND COMPUTING↗

GASNet-EX Memory Kinds: Support for Device Memory in PGAS Programming Models

There is an emerging need for adaptive, lightweight communication in irregular HPC applications at exascale, where GPU accelerators provide the majority of available compute cycles. To address this need, Lawrence Berkeley National Lab is developing a programming system to support distributed-memory HPC application development using the Partitioned Global Address Space (PGAS) model. This work includes two major components: UPC++ and GASNet-EX. UPC++ is a C++ template library providing Remote Memory Access (RMA) and Remote Procedure Call (RPC) communication interfaces. GASNet-EX is a portable, high-performance communication middleware library, used by the implementations of UPC++ and many other PGAS programming models. We describe recent advances in GASNet-EX to efficiently implement zero-copy Remote Memory Access (RMA) communication to and from memory on accelerator devices such as GPUs. We demonstrate performance improvements via benchmark results from UPC++ (on Summit) and the Legion programming system (on DGX-1), both using GASNet-EX for communication.

Hargrove, Paul H↗

Method and apparatus for selective and power-aware memory error protection and memory management

A method for providing selective memory error protection responsive to a predictable failure notification associated with at least one portion of a memory in a computing system includes: obtaining an active error correcting code (ECC) configuration corresponding to the portion of the memory; determining whether the active ECC configuration is sufficient to correct at least one error in the portion of the memory affected by the predictable failure notification; when the active ECC configuration is insufficient to correct the error, determining whether data corruption can be tolerated by an application running on the computing system; when data corruption cannot be tolerated by the application, determining whether a stronger ECC level is available and, if a stronger ECC level is available, increasing a strength of the active ECC configuration; and when data corruption can be tolerated, performing page reassignment and aggregation of non-critical data.

97 MATHEMATICS AND COMPUTING↗

The roles of the dielectric constant and the relative level of conduction band of high-k composite with Si in improving the memory performance of charge-trapping memory devices

The memory structures Pt/Al{sub 2}O{sub 3}/(TiO{sub 2}){sub x}(Al{sub 2}O{sub 3}){sub 1−x}/Al{sub 2}O{sub 3}/p-Si(nominal composition x = 0.05, 0.50 and 0.70) were fabricated by using rf-magnetron sputtering and atomic layer deposition techniques, in which the dielectric constant and the bottom of the conduction band of the high-k composite (TiO{sub 2}){sub x}(Al{sub 2}O{sub 3}){sub 1−x} were adjusted by controlling the partial composition of Al{sub 2}O{sub 3}. With the largest dielectric constant and the lowest deviation from the bottom of the conduction band of Si, (TiO{sub 2}){sub 0.7}(Al{sub 2}O{sub 3}){sub 0.3} memory devices show the largest memory window of 7.54 V, the fast programming/erasing speed and excellent endurance and retention characteristics, which were ascribed to the special structural design, proper combination of dielectric constant and band alignment in the high-k composite (TiO{sub 2}){sub 0.7}(Al{sub 2}O{sub 3}){sub 0.3}.

36 MATERIALS SCIENCE↗

Multilevel characteristics and memory mechanisms for nonvolatile memory devices based on CuInS{sub 2} quantum dot-polymethylmethacrylate nanocomposites

Nonvolatile memory devices based on CuInS{sub 2} (CIS) quantum dots (QDs) embedded in a polymethylmethacrylate (PMMA) layer were fabricated using spin-coating method. The memory window widths of the capacitance-voltage (C-V) curves for the Al/CIS QDs embedded in PMMA layer/p-Si devices were 0.3, 0.6, and 1.0 V for sweep voltages of ±3, ±5, and ±7 V, respectively. Capacitance-cycle data demonstrated that the charge-trapping capability of the devices with an ON/OFF ratio value of 2.81 × 10{sup −10} was maintained for 8 × 10{sup 3} cycles without significant degradation and that the extrapolation of the ON/OFF ratio value to 1 × 10{sup 6} cycles converged to 2.40 × 10{sup −10}, indicative of the good stability of the devices. The memory mechanisms for the devices are described on the basis of the C-V curves and the energy-band diagrams.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

Ion fluxes and memory effects in an Ar–O 2 modulated radiofrequency-driven atmospheric pressure plasma jet

In this work we used molecular beam mass spectrometry to characterize ion fluxes produced by a modulated radiofrequency (RF)-driven atmospheric pressure plasma jet operating in a homogeneous gas environment (Ar + 1% O 2 ). The influence of the RF modulation frequency (100 Hz to 20 kHz) on the ion fluxes was investigated by time-resolved measurements, and the lifetimes of the dominant ions, O 2 + , NO + , O − , O 2 − and O 3 − , were found to be 28 ± 2, 117 ± 8, 7.3 ± 0.4, 17 ± 1 and 23 ± 2 μs, respectively. The absolute ion densities in the near afterglow region were found to be of the order of 1011 cm−3. Significant differences in the dynamics of the positive and negative ions were found; these are explained by the presence of electrons at similar densities in the afterglow produced by electron detachment reactions from negative ions due to the large concentrations of atomic oxygen and singlet delta oxygen. Transitions in ion flux dynamics for different modulation frequencies and at the startup of the plasma were analyzed together with intensified charge coupled device images recording the plasma propagation in order to assess the dynamics of plasma plume propagation and how it is impacted by ‘memory effects’. Quantitative measurements of the ion densities enabling these memory effects are reported. The results in this paper highlight the tremendous impact of memory effects on plasma propagation and the corresponding pre-ionization.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗