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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Enhancing EV Motor Design Through Knowledge-Based AI and Hierarchical Fuzzy Logic Model

This work presents a novel approach to optimizing electric vehicle motor design through the integration of Knowledge-Based Artificial Intelligence (KB-AI) and Hierarchical Fuzzy Logic. Traditional motor design processes are time-intensive, relying heavily on iterative simulations and domain-specific expertise. These processes are further complicated by the nonlinear relationships between key design parameters. The proposed framework addresses these challenges by systematically encoding expert knowledge from scientific literature into a fuzzy logic system, allowing for the efficient handling of complex design variables. The hierarchical fuzzy logic model reduces computational complexity by decomposing the nonlinear relationships into manageable rule sets while maintaining design accuracy. The proposed methodology was applied to the design of a 100 kW motor, yielding optimal values for key parameters. This resulted in a compact motor design with a volume of 2.2 liters, showcasing the framework’s ability to deliver high-performance, application-specific motor configurations.

Kumar, Praveen [ORNL] (ORCID:0000000291877857)↗
DOE OSTI2022

Host-region parameters for an adjustable model for crustal earthquakes to facilitate the implementation of the backbone approach to building ground-motion logic trees in probabilistic seismic hazard analysis

The backbone approach to constructing a ground-motion logic tree for probabilistic seismic hazard analysis (PSHA) can address shortcomings in the traditional approach of populating the branches with multiple existing, or potentially modified, ground-motion models (GMMs) by rendering more transparent the relationship between branch weights and the resulting distribution of predicted accelerations. To capture epistemic uncertainty in a tractable manner, there are benefits in building the logic tree through the application of successive adjustments for differences in source, path, and site characteristics between the host region of the selected backbone GMM and the target region for which the PSHA is being conducted. The implementation of this approach is facilitated by selecting a backbone GMM that is amenable to such host-to-target adjustments for individual source, path, and site characteristics. The NGA-West2 GMM of Chiou and Youngs (CY14) has been identified as a highly adaptable model for crustal seismicity that is well suited to such adjustments. Rather than using generic source, path, and site characteristics assumed appropriate for the host region, the final suite of adjusted GMMs for the target region will be better constrained if the host-region parameters are defined specifically on the basis of their compatibility with the CY14 backbone GMM. To this end, making use of a recently developed crustal shear-wave velocity profile consistent with CY14, we present an inversion of the model to estimate the key source and path parameters, namely the stress parameter and the anelastic attenuation. With these outputs, the effort in constructing a ground-motion logic tree for any PSHA dealing with crustal seismicity can be focused primarily on the estimation of the target-region characteristics and their associated uncertainties. The inversion procedure can also be adapted for any application in which different constraints might be relevant.

Stafford, Peter J.↗
DOE OSTI2025

Rapid Inference of Logic Gate Neural Networks for Anomaly Detection in High Energy Physics

The increasing data rates and complexity of detectors at the Large Hadron Collider (LHC) necessitate fast and efficient machine learning models, particularly for rapid selection of what data to store, known as triggering. Building on recent work in differentiable logic gates, we present a public implementation of a Convolutional Differentiable Logic Gate Neural Network (CLGN). We apply this to detecting anomalies at the Level-1 Trigger at CMS using public data from the CICADA project. We demonstrate that the CLGN achieves physics performance on par with or superior to conventional quantized neural networks. We also synthesize an LGN for a Field-Programmable Gate Array (FPGA) and show highly promising FPGA characteristics, notably zero Digital Signal Processor (DSP) resource usage. This work highlights the potential of logic gate networks for high-speed, on-detector inference in High Energy Physics and beyond.

FOS: Physical sciences↗
DOE OSTI2022

Memory forensic analysis of a programmable logic controller in industrial control systems

In industrial control systems (ICS), programmable logic controllers (PLCs) are used to automate physical processes such as nuclear plants and power grid stations, and are often subject to cyber attacks. As in conventional IT domain, the memory analysis of the PLCs can help answer important forensic questions about the attack, such as the presence of malicious firmware, injection of modified control logic (the program running on the PLC), and manipulation of I/O devices (e.g., sensors and actuators). Unlike conventional IT domain, PLCs have heterogeneous hardware architecture, proprietary firmware and control software, making it challenging to employ a unified framework for their memory forensics. For merely extracting artifacts of forensic importance, reverse-engineering the firmware is a tedious task, and the effort needs to be repeated for every PLC model. As a community, a step-wise approach to tackle this challenge is to analyze the memory of specific PLCs, and subsequently find a generic framework applicable to all PLCs. Our work is a step forward in this direction. By following a methodology that focuses on the functional layer of PLCs instead of reverse engineering the firmware, we analyze the digital forensic artifacts available in a common PLC, Allen-Bradley ControlLogix 1756-L61. Before diving into the memory dump, we analyze the PLC control software to create a list of important artifacts that are sure to exist in the PLC memory dump. The approach employs a setup where PLC control software RSLogix-5000 is connected to the PLC, and the memory dump can be obtained as and when needed. We create test cases that sequentially highlight each category of artifacts, followed by an examination of the resultant impact on memory. After attaining the listed artifacts, we employ conventional string and known data searches to extract interesting information present in this PLC's memory. The memory analysis profile, presented as a Python library and shared with the community, can help a forensic investigator to readily extract forensic artifacts from the same model's controller. The adopted approach may help researchers in creating memory profile of other PLCs, and ultimately formulating a generic PLC memory analysis framework.

Rais, Muhammad Haris↗
DOE OSTI2023

Towards generic memory forensic framework for programmable logic controllers

A Programmable Logic Controller (PLC) is a microprocessor-based controller that is used to automate physical processes in critical infrastructure and various other industries and manufacturing sectors. Initially, PLCs were completely isolated from the Internet, and cyber security was not incorporated at the time of development. The introduction of industry 4.0 and the evolution of ICS systems to communicate over public IP addresses from the Internet enhanced productivity and efficiency, but Internet connectivity exposed the systems and their vulnerabilities, which led to an increase in cyber attacks. When a system is sabotaged/compromised, security analysts need to get to the root cause of the attack as quickly as possible to recover the system. To do so, memory forensic analysis is critical to provide a unique insight into the run-time memory activities and extract a reliable source of evidence. In this paper, we analyze the memory structure of the Schneider Electric Modicon M221 PLC. To build a memory profile, we reverse engineer the communication protocol and conduct differential analysis to gain knowledge about the structure of the memory and the low-level representation of control logic instructions. We then identify dynamic and static memory regions by modifying different project fields and conducting differential analysis, which allows us to identify boundaries of critical memory structures and extract important forensic artifacts that can be found in the memory. The Python implementation of the memory profile can help reduce the time and effort required for manual analysis in case of cyber incident or system failure.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Fail-Safe Logic Design Strategies Within Modern FPGA Architectures

Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.

Bhakta, Priya A. [Univ. of New Mexico, Albuquerque↗
DOE OSTI2022

Logic operations with active topological defects

Logic operations performed by semiconductor-based transistors are the basis of modern computing. There is considerable interest in creating autonomous materials systems endowed with the capability to make decisions. In this work, we introduce the concept of using topological defects in active matter to perform logic operations. When an extensile active stress in a nematic liquid crystal is turned on, +1/2 defects can self-propel, in analogy to electron transport under a voltage gradient. By relying on hydrodynamic simulations of active nematics, we demonstrate that patterns of activity, when combined with surfaces imparting certain orientations, can be used to control the formation and transport of +1/2 defects. We further show that asymmetric high- and low-activity patterns can be used to create effective defect gates, tunnels, and amplifiers. The proposed active systems offer the potential to perform computations and transmit information in active soft materials, including actin-, tubulin-, and cell-based systems.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2021

Recognition Method of Vehicle Cluster Situation Based on Set Pair Logic considering Driver’s Cognition

The recognition of vehicle cluster situations is one of the critical technologies of advanced driving, such as intelligent driving and automated driving. The accurate recognition of vehicle cluster situations is helpful for behavior decision‐making safe and efficient. In order to accurately and objectively identify the vehicle cluster situation, a vehicle cluster situation model is proposed based on the interval number of set pair logic. The proposed model can express the traffic environment’s knowledge considering each vehicle’s characteristics, grouping relationships, and traffic flow characteristics in the target vehicle’s interest region. A recognition method of vehicle cluster situation is designed to infer the traffic environment and driving conditions based on the connection number of set pair logic. In the proposed model, the uncertainty of the driver’s cognition is fully considered. In the recognition method, the relative uncertainty and relative certainty of driver’s cognition, traffic information, and vehicle cluster situation are fully considered. The verification results show that the proposed recognition method of vehicle cluster situations can realize accurate and objective recognition. The proposed anthropomorphic recognition method could provide a basis for vehicle autonomous behavior decision‐making.

Liu, Shijie↗
DOE OSTI2020

Logic in Memory Emulator

Logic in Memory Emulator (LiME) is a hardware/software tool specially designed for memory system evaluation and experiment. Emerging memories display a wide range of bandwidths, latencies, and capacities, making it challenging for the computer architect to navigate the design space of potential memory configurations, and for the application developer to assess performance implications of using such memories. With the LiME framework, architectural ideas can be prototyped in great detail yet with sufficient performance to support realistic evaluation on long running applications. LiME consists of two fundamental components: 1) the hardware and OS infrastructure for the emulator, and 2) a suite of benchmark applications to assist in characterizing the performance of current and future computer architectures. Some of the applications have been collected from other open source projects. Uses: Logging, replay and analysis of an application's memory behavior Evaluate impact of emerging memory technology on application performance. Emulate complex memory interactions in whole applications orders of magnitude faster than software simulation. Emulate acceleration hardware co-located with the memory subsystem. Features: Capture and log external memory accesses to a separate off-chip memory device without affecting application execution. Memory traces include the address, length, timestamp, and optionally the data for each transaction. Captured trace data can be saved to an SD card for off-line analysis. Configure a wide range of memory latencies in sub-nanosecond increments that encompass highbandwidth and storage class memories. Specify regions of interest (ROI) in applications to reduce the amount of trace data captured for analysis. Currently supports execution on Xilinx Zynq SoC which integrates an ARM processor with FPGA logic on a single device. Applications can be run under Linux or in bare metal mode on the ARM cores.

Jain, AbhishekK↗
DOE OSTI2022

Automated Production of Optimization-Based Control Logics for Dynamic Facade Systems, with Experimental Application to Two-Zone External Venetian Blinds

The primary goal of this research is to devise a system that produces controllers for complex fenestration systems that perform nearly as well as Model Predictive Control but at a level of cost and implementation complexity that rivals simple heuristic controls. To this end, a cloud-based automated controller production system has been set up for a motorized external Venetian blind device, with a simple web interface that can be used by non-experts. The computation cost per controller is in the range of a few dollars, and the control logic is simple enough to be implemented on small and cheap distributed controllers. The web interface allows the user to specify some details of their particular building and window configuration, including orientation, latitude, interior geometries, and lighting and HVAC system parameters. Upon submittal, a cloud-based system configures the necessary files and commands, and then runs thousands of optimizations with them. Once the calculations are finished, the system produces a lookup table and interpolation-based controller scripts that can be used on a simple and cheap distributed controller. This paper describes the underlying models and optimization processes. It also describes the resulting control logics for two cases tested at Lawrence Berkeley National Laboratory’s Advanced Windows Testbed Facility: illuminance maximization subject to glare constraints; and lighting + HVAC energy minimization. The performance of the model-based controllers produced by the automated web-based system are compared to a heuristic ‘block beam’ controller in physical experiments at the Testbed. The experimental results are supplemented by simulation experiments with the same configuration as the Testbed. The results show the illuminance maximizing controller significantly outperforms the heuristic controller in terms of glare avoidance, and also outperforms it in terms of hours of daylight autonomy. The energy minimizing controller also outperforms the heuristic controller. This paper also discusses how the web-based system may be extended to consider other configurations, such as electrochromic windows and thermally massive HVAC systems. Potential roles for this type of system within the building design and construction industry are discussed.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2024

Applications of Fuzzy Logic for Tritium Sensing Technology

Fuzzy Logic is a mathematical method that can represent human-like decisions by analyzing vagueness. The project is a practical approach for evaluating sensors using a fuzzy group best-worst method. Results What is the best sensor? The fuzzy logic methods give an answer to that through a selection system. The relationship between the inputs and the outputs gives consumers an understanding of how the best sensor was found through a scoring of each quality/criteria and their corresponding sub-criteria through expert opinion.

Holman, Allyson↗
DOE OSTI2024

Applications of fuzzy logic and best-worst method for tritium sensor selection

Accurate assessment of tritium as a fuel source is critical in fusion reactions, necessitating effective sensor evaluation methods. This study investigates a multi-criteria decision-making framework for selecting tritium sensors, integrating fuzzy logic to enhance decision quality. Initial attempts at applying fuzzy logic were found to be too elementary and failed to capture the complexity of multi-criteria selection; this prompted a refined approach that incorporated expert insights and advanced ranking techniques for sensor evaluation. The research used a two-stage methodology. In the first stage, important criteria and sub-criteria for sensor performance were identified and defined. These criteria were then weighted and scored using a fuzzy best-worst method, drawing upon expert opinions to ensure relevance and validity. The second stage involved interpreting information about varying sensors to rank them based on their overall criteria scores, encouraging the selection of the most suitable options. The result of the study is a proposed method for effective sensor selection in fusion reactors, which in turn will significantly improve the reliability of tritium monitoring in fusion applications.

11 NUCLEAR FUEL CYCLE AND FUEL MATERIALS↗
DOE OSTI2021

Comprehension of Spatial Constraints by Neural Logic Learning from a Single RGB-D Scan

Autonomous industrial assembly relies on the precise measurement of spatial constraints as designed by computer-aided design (CAD) software such as SolidWorks. This paper proposes a framework for an intelligent industrial robot to understand the spatial constraints for model assembly. An extended generative adversary network (GAN) with a 3D long short-term memory (LSTM) network was designed to composite 3D point clouds from a single RGB-D scan. The spatial constraints of the segmented point clouds are identified by a neural-logic network that incorporates general knowledge of spatial constraints in terms of first-order logic. The model was designed to comprehend a complete set of spatial constraints that are consistent with industrial CAD software, including left, right, above, below, front, behind, parallel, perpendicular, concentric, and coincident relations. The accuracy of 3D model composition and spatial constraint identification was evaluated by the RGB-D scans and 3D models in the ABC dataset. The proposed model achieved 57.23% intersection over union (IoU) in 3D model composition, and over 99% in comprehending all spatial constraints.

Wang, Dali↗
DOE OSTI2023

Machine Learning 5G Attack Detection in Programmable Logic

Machine learning-assisted network security may significantly contribute to securing 5G components. However, machine learning network security inference speeds generally require tens to hundreds of milliseconds thereby introducing significant latency in 5G operations. The inference latency can be reduced by deploying the machine learning model to programmable logic in a field programmable gate array (FPGA) at the cost of a small loss in accuracy. In order to quantify this loss, as well as to establish baseline performance inference speeds for programmable logic implementations, this work explores an autoencoder and a ß-variational autoencoder deployed on two different FPGA evaluation boards and compares accuracy and performance against an NVIDIA A100 GPU implementation. A publicly available 5G dataset containing 10 types of attacks along with normal traffic is introduced as part of the evaluation.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Software and Firmware-logic Design for the PIP-II Machine Protection System Mode and Configuration Control at Fermilab

The PIP-II Machine Protection System (MPS) requires a dedicated set of tools for configuration control and management of the machine modes and beam modes of the accelerator. The protection system reacts to signals from various elements of the machine according to rules established in a setup database in the form of a Look-Up-Table filtered by the program Mode Controller. This is achieved in accordance with commands from the operator and governed by the firmware logic of the MPS. This paper describes the architecture, firmware logic, and implementation of the program mode controller.

43 PARTICLE ACCELERATORS↗
DOE OSTI2022

Tunable quantum logic gate on photonic qubits with a ladder emitter

We describe how a ladder emitter can implement a tunable quantum logic gate on photonic qubits encoded in the frequency basis. The ground-to-first excited state of the ladder emitter interacts with the control photon, and the first-to-second excited state transition interacts with the target photon. By controlling the relative detuning between the target photon and the first-to-second excited state transition of the ladder emitter, we enable any controlled-phase operation from 0 to π. We derive analytical formulas for the performance of the gate through the S-matrix formalism as well as describe the mechanism intuitively. This gate is deterministic, does not utilize any active control, and needs only a single ladder emitter, enabling low-footprint and more efficient decomposition of quantum circuits, especially the quantum Fourier transform. We suggest multiple potential systems for physical realization of our proposal, such as lanthanide ions embedded in Purcell-enhanced cavities. We expect these results to motivate further interest in photonic quantum information processing with designer emitters.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Machine Learning Models for Network Traffic Classification in Programmable Logic

Network traffic classification via machine learning on network packet payloads has emerged as an active area of research for network security due to the high accuracy machine learning models have achieved in classifying payloads. For effective deployment as part of network security, these machine learning models must not only classify malicious packet payloads accurately, they must also identify anomalous payloads and perform inference at speeds generally faster than 10,000 packets per second to be effective. This work explores the in- ference speeds and accuracy of several neural network models implemented in programmable logic on various field programmable gate arrays (FPGA) including the Xilinx VC1902 and Xilinx Zynq Ultrascale+. This work also presents the design and performance of both an autoencoder and variational autoencoder programmed on the FPGA for identifying anomalous packet payloads. The performance benefits of the FPGA implementation for this type of packet payload inspection driven by machine learning are compared against graphics processing unit (GPU) inference implementations run on two state-of-the-art datacenter GPU devices, the NVIDIA V100 and A100. The model accuracy difference between the FPGA and GPU implementations was found to be 4% or less while the Xilinx VC1902 outperformed both the NVIDIA V100 and A100 for inference speeds on all the models explored except the variational autoencoder.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications

Here this paper presents a superconducting, magnetically-coupled, shuttle-flux shift register (SF-SR) that stores single flux quantum (SFQ) pulses. This shift register has a DC bias operating margin of ±34% at 10 GHz, with a power dissipation of 3.6 μW and 38% fewer Josephson junctions (JJs) when scaled up to multiple stages compared to a data flip-flop (DFF) based shift register. The clock input is inductively coupled and is independent from the data input. We then present three applications for our SF-SR. In the first application, we add two non-destructive readout (NDRO) cells to construct a buffer that temporarily stores the temporal information of a series of race logic (RL) pulses. The second application is a pseudo-random number generator based on a linear function shift register (LFSR). The third application is N parallel SF-SRs that can act similar to a deserializer or instead can emulate a single SF-SR of N times higher clock frequency. These three applications motivate deep shift registers with many shifting intervals, which our SF-SR can implement with fewer JJs and lower power consumption compared to DFF-based shift registers.

42 ENGINEERING↗