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DOE OSTI2024

Transmission Interconnection Roadmap: Transforming Bulk Transmission Interconnection by 2035

The U.S. electricity system is amid a rapidly occurring and widespread energy transition. Regional, Tribal, state, and customer demand for new energy resources, combined with favorable policies, is driving a rapid rise of interconnection requests. Interconnection processes will need to evolve to handle this larger number of requests today and into the future, as policy and economic drivers continue to motivate significant resource development. This roadmap identifies and organizes nearer- and longer-term solutions to enable transmission interconnection processes to meet this expected demand, and it is intended for a diverse audience of stakeholders participating within transmission interconnection processes. The roadmap is a result of the Interconnection Innovation e-Xchange (i2X) program launched by the U.S. Department of Energy (DOE) in June 2022 to convene stakeholders and address interconnection challenges. The roadmap is organized into four primary goal areas, each important to the overall i2X mission to enable a simpler, faster, and fairer interconnection of clean energy resources while enhancing the reliability, resiliency, and security of our electric grid. The first goal aims to improve interconnection data transparency, to aid interconnection customers’ ability to screen and site potential projects, better enable third-party modeling, facilitate more process automation, enhance competition while ensuring equitable outcomes, and enable benchmarking, tracking, and auditing of interconnection processes and reforms. The second goal covers solutions to improve queue management practices, affected system studies, fair processes, and workforce development. The third goal incorporates solutions that aim to improve cost allocation, reduce costs to electricity consumers, enhance the coordination between transmission planning and the interconnection process, and optimize the rightsizing of transmission investment through improvements in interconnection studies. The fourth and final goal aims to reduce the performance issues not identified during interconnection studies by updating technical requirements within interconnection studies, models, and tools while also improving industry interconnection standards.

24 POWER TRANSMISSION AND DISTRIBUTION↗

NASA NTRS1995

A decentralized software bus based on IP multicas ting

We describe decentralized reconfigurable implementation of a conference management system based on the low-level Internet Protocol (IP) multicasting protocol. IP multicasting allows low-cost, world-wide, two-way transmission of data between large numbers of conferencing participants through the Multicasting Backbone (MBone). Each conference is structured as a software bus -- a messaging system that provides a run-time interconnection model that acts as a separate agent (i.e., the bus) for routing, queuing, and delivering messages between distributed programs. Unlike the client-server interconnection model, the software bus model provides a level of indirection that enhances the flexibility and reconfigurability of a distributed system. Current software bus implementations like POLYLITH, however, rely on a centralized bus process and point-to-point protocols (i.e., TCP/IP) to route, queue, and deliver messages. We implement a software bus called the MULTIBUS that relies on a separate process only for routing and uses a reliable IP multicasting protocol for delivery of messages. The use of multicasting means that interconnections are independent of IP machine addresses. This approach allows reconfiguration of bus participants during system execution without notifying other participants of new IP addresses. The use of IP multicasting also permits an economy of scale in the number of participants. We describe the MULITIBUS protocol elements and show how our implementation performs better than centralized bus implementations.

Callahan, John R.↗

DOE OSTI2024

P38 heterogeneous multi-tiled system with support for message queues (MoSAIC) v0.1

The proposed system is written in the hardware description language (HDL) verilog targeting an FPGA board. It is intended as a testbed to explore architecture tradeoffs in multi-tiled heterogeneous architectures. Although we target FPGAs, the system can be implemented as a monolithic SoC or a package comprised of many chiplets that are interconnected in the same package using a NoC. The proposed NoC is lightweight and follows an axi-lite interface. The endpoints of the NoC are a heterogeneous mix of "tiles" as endpoints that are general purpose processors, fixed function accelerators, and programmable accelerators. We assume that the network interfaces for the NoC endpoints are all addressable in a global name-space in that they represent an address range (for memory addresses) or a range of unique identifiers that are associated with each individual tile. This makes the functionality abstract from the standpoint of the NoC design details. Message queues offer a direct inter-processor interface between peer general purpose cores and diverse accelerators that comprise an SoC. Although they share the same NoC infrastructure for inter-tile communication within an SoC or SiP, the hardware message queues bypass the memory hierarchy and thus do not pollute the memory state or invoke the cache coherence mechanism.

Gonzalez, LouisaPatricia↗

NASA NTRS2011

Data Interconnection Exploration

This project involves innovating the way the Quality Assurance organization at the Jet Propulsion Laboratory (JPL) tracks the receiving inspection of JPL Critical Items (JCI) procured from suppliers. The Quality Assurance organization uses a Microsoft Access based front-end to enter items into an inspection queue. The current design has grown to be much more than was expected when the inspection queue system was created in 2007. The goal is to migrate to a web based solution that will allow the handling of more data, multiple input interfaces, and customizable display options. This has been achieved by implementing a divided tables scheme, the use of ColdFusion programming language, and the usage of Web 2.0 technologies such as AJAX and jQuery. These updates will allow for future expansion as well as the standardization of inspection queues for the Quality Assurance organization. When engineers and scientists order flight hardware, they cannot use it straight away. After a spacecraft or a satellite has been launched, it will be impossible to repair; therefore, the parts used must be inspected to make sure they are operating correctly and within the required specifications. The task of inspecting these JPL Critical Items (JCI) falls on the Quality Assurance organization. One of the tools the receiving inspection group uses is a database to maintain a queue of inspections that need to be done and of inspections that have been completed. The current Access interface has worked well but increased amounts of data, multiple input interfaces, and changes to how data is handled have made it necessary to seek a new way of organizing items for inspection. In addition, the different inspection groups have recently been merged and each has different ways of keeping track of inspection information. The ultimate goal is for the new group to have one shared inspection queue and website. To achieve this goal, I have been working with Ian Luczon of Procurement Quality Assurance and 3 Myers Hawkins, another intern, to not only create the new queue for receiving inspection but also a central web portal for the newly combined inspection group.

flight hardware↗

NASA NTRS2006

CAISSON: Interconnect Network Simulator

Cray response to HPCS initiative. Model future petaflop computer interconnect. Parallel discrete event simulation techniques for large scale network simulation. Built on WarpIV engine. Run on laptop and Altix 3000. Can be sized up to 1000 simulated nodes per host node. Good parallel scaling characteristics. Flexible: multiple injectors, arbitration strategies, queue iterators, network topologies.

network simulation↗

DOE OSTI2025

The DUNE-DAQ Application Framework

The deep underground neutrino experiment (DUNE) is a next-generation neutrino experiment that will probe the properties of these elusive particles with unparalleled precision. It will also act as an observatory for neutrino bursts caused by nearby supernovae, in the event that one occurs, while the experiment is in operation. Given these goals, the DUNE trigger and DAQ system must be able to maintain extremely high uptime and provide a path for full readout of the detectors for very long times (up to 100 s). To achieve these ends, we have designed the DUNE DAQ system around a flexible “application framework,” which provides a modular interface for specific tasks while handling the interconnections between them. The application framework collects modules into applications, which can then be interacted with as units by the control, configuration, and monitoring systems. One of the key features of the framework is its communication abstraction layer, which allows for modules to interact with both internal queues and external network connections with a single transport-agnostic interface. We will report on the architecture and features of the framework.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2024

The DUNE DAQ Application Framework

The Deep Underground Neutrino Experiment (DUNE) is a next-generation neutrino experiment that will probe the properties of these elusive particles with unparalleled precision. It will also act as an observatory for neutrino bursts caused by nearby supernovae, in the event that one occurs while the experiment is in operation. Given these goals, the DUNE trigger and DAQ system must be able to maintain extremely high uptime and provide a path for full readout of the detectors for very long times (up to 100s). To achieve these ends, we have designed the DUNE DAQ system around a flexible “application framework”, which provides a modular interface for specific tasks while handling the interconnections between them. The application framework collects modules into applications which can then be interacted with as units by the control, configuration and monitoring systems. One of the key features of the framework is its communications abstraction layer, which allows for modules to interact with both internal queues and external network connections with a single transport-agnostic interface. We will report on the architecture and features of the framework.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

NASA NTRS1992

Dynamically-allocated multi-queue buffers for VLSI communication switches

Several buffer structures are discussed and compared in terms of implementation complexity, interswitch handshaking requirements, and their ability to deal with variations in traffic patterns and message lengths. A new design of buffers is presented that provide non-FIFO message handling and efficient storage allocation for variable size packets using linked lists managed by a simple on-chip controller. The new buffer design is evaluated by comparing it to several alternative designs in the context of a multistage interconnection network. The present modeling and simulations show that the new buffer outperforms alternative buffers and can thus be used to improve the performance of a wide variety of systems currently using less efficient buffers.

Tamir, Yuval↗

NASA NTRS1992

NCC Simulation Model: Simulating the operations of the network control center, phase 2

The simulation of the network control center (NCC) is in the second phase of development. This phase seeks to further develop the work performed in phase one. Phase one concentrated on the computer systems and interconnecting network. The focus of phase two will be the implementation of the network message dialogues and the resources controlled by the NCC. These resources are requested, initiated, monitored and analyzed via network messages. In the NCC network messages are presented in the form of packets that are routed across the network. These packets are generated, encoded, decoded and processed by the network host processors that generate and service the message traffic on the network that connects these hosts. As a result, the message traffic is used to characterize the work done by the NCC and the connected network. Phase one of the model development represented the NCC as a network of bi-directional single server queues and message generating sources. The generators represented the external segment processors. The served based queues represented the host processors. The NCC model consists of the internal and external processors which generate message traffic on the network that links these hosts. To fully realize the objective of phase two it is necessary to identify and model the processes in each internal processor. These processes live in the operating system of the internal host computers and handle tasks such as high speed message exchanging, ISN and NFE interface, event monitoring, network monitoring, and message logging. Inter process communication is achieved through the operating system facilities. The overall performance of the host is determined by its ability to service messages generated by both internal and external processors.

Benjamin, Norman M.↗

NASA NTRS1994

Regular Topologies for Gigabit Wide-Area Networks

In general terms, this project aimed at the analysis and design of techniques for very high-speed networking. The formal objectives of the project were to: (1) Identify switch and network technologies for wide-area networks that interconnect a large number of users and can provide individual data paths at gigabit/s rates; (2) Quantitatively evaluate and compare existing and proposed architectures and protocols, identify their strength and growth potentials, and ascertain the compatibility of competing technologies; and (3) Propose new approaches to existing architectures and protocols, and identify opportunities for research to overcome deficiencies and enhance performance. The project was organized into two parts: 1. The design, analysis, and specification of techniques and protocols for very-high-speed network environments. In this part, SRI has focused on several key high-speed networking areas, including Forward Error Control (FEC) for high-speed networks in which data distortion is the result of packet loss, and the distribution of broadband, real-time traffic in multiple user sessions. 2. Congestion Avoidance Testbed Experiment (CATE). This part of the project was done within the framework of the DARTnet experimental T1 national network. The aim of the work was to advance the state of the art in benchmarking DARTnet's performance and traffic control by developing support tools for network experimentation, by designing benchmarks that allow various algorithms to be meaningfully compared, and by investigating new queueing techniques that better satisfy the needs of best-effort and reserved-resource traffic. This document is the final technical report describing the results obtained by SRI under this project. The report consists of three volumes: Volume 1 contains a technical description of the network techniques developed by SRI in the areas of FEC and multicast of real-time traffic. Volume 2 describes the work performed under CATE. Volume 3 contains the source code of all software developed under CATE.

Shacham, Nachum↗