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At least 55 records · Page 3

Simulations of transition and turbulence on the Navier-Stokes computer

The Navier-Stokes Computer (NSC) consists of multiple local memory parallel processors interconnected in a hypercube network. Efficient implementation of algorithms on the NSC thus requires the effective utilization of both the coarse and fine grain paralelism inherent in the architectural design. The basic approach to implementing an algorithm on the NSC is presented herein. The particular finite-difference algorithm considered was developed for performing transition and turbulence simulations by direct solution of the time-dependent incompressible Navier-Stokes equations. The suitability of this algorithm for performing simulations of the isotropic turbulence problem is verified from computations performed on a Cray 2. Projected timing results for the algorithm on the NSC itself are presented for both the isotropic turbulence and laminar turbulent transition problems.

Krist, S. E.↗

Lightweight concentrator module with 30 percent AM0 efficient GaAs/GaSb tandem cells

A concept is presented for an aerospace concentrator module with lightweight domed lenses and 30 percent AM0 efficient GaAs/GaSb tandem solar cell circuits. The performance of transparent GaAs cells is reviewed. NASA's high-altitude jet flight calibration data for recent GaSb cells assembled with bulk GaAs filters are reported, along with subsequent Boeing and NASA measurements of GaSb I-V performance at various light levels and temperatures. The expected performance of a basic two-terminal tandem concentrator circuit with three-to-one voltage matching is discussed. All of the necessary components being developed to assemble complete flight test coupons are shown. Straightforward interconnect and assembly techniques yield voltage matched circuits with near-optimum performance over a wide temperature range.

Avery, J. E.↗

High Current ESD Test of Advanced Triple Junction Solar Array Coupon

A test was conducted on an Advanced Triple Junction (ATJ) coupon that was part of a risk reduction effort in the development of a high-powered solar array design by SSL. The ATJ coupon was a small, 4-cell, two-string configuration that has served as the basic test coupon design used in previous SSL environmental aging campaigns. The coupon has many attributes of the flight design; e.g., substrate structure with graphite face sheets, integrated by-pass diodes, cell interconnects, RTV grout, wire routing, etc. The objective of the present test was to evaluate the performance of the coupon after being subjected to induced electrostatic discharge testing at two string voltages (100 V, 150 V) and four array current (1.65 A, 2.0 A, 2.475 A, and 3.3 A). An ESD test circuit, unique to SSL solar array design, was built that simulates the effect of missing cells and strings in a full solar panel with special primary arc flashover circuitry. A total of 73 primary arcs were obtained that included 7 temporary sustained arcs (TSA) events. The durations of the TSAs ranged from 50 μs to 2.9 ms. All TSAs occurred at a string voltage of 150 V. Post-test Large Area Pulsed Solar Simulator (LAPSS), Dark I-V, and By-Pass Diode tests showed that no degradation occurred due to the TSA events. In addition, the post-test insulation resistance measured was > 50 G-ohms between cells and substrate. These test results indicate a robust design for application to a high-current, high-power mission application.

Wright, K. H.↗

High Current ESD Test of Advanced Triple Junction Solar Array Coupon

Testing was conducted on an Advanced Triple Junction (ATJ) coupon that was part of a risk reduction effort in the development of a high-powered solar array design by Space Systems/Loral, LLC (SSL). The ATJ coupon was a small, 4-cell, two-string configuration that has served as the basic test coupon design used in previous SSL environmental aging campaigns. The coupon has many attributes of the flight design; e.g., substrate structure with graphite face sheets, integrated by-pass diodes, cell interconnects, RTV grout, wire routing, etc. The objective of the present test was to evaluate the performance of the coupon after being subjected to induced electrostatic discharge (ESD) testing at two string voltages (100 V, 150 V) and four array currents (1.65 A, 2.0 A, 2.475 A, and 3.3 A). An ESD test circuit, unique to SSL solar array design, was built that simulates the effect of missing cells and strings in a full solar panel with special primary arc flashover circuitry. A total of 73 primary arcs were obtained that included 7 temporary sustained arcs (TSA) events. The durations of the TSAs ranged from 50 micro-seconds to 2.75 milli-seconds. All TSAs occurred at a string voltage of 150 V. Post-test Large Area Pulsed Solar Simulator (LAPSS), Dark I-V, and By-Pass Diode tests showed that no degradation occurred due to the TSA events. In addition, the post-test insulation resistance measured was > 50 G-ohms between cells and substrate. These test results indicate a robust design for application to a high-current, high-power mission.

Wright, Kenneth H., Jr.↗

High Current ESD Test of Advanced Triple Junction Solar Array Coupon

A test was conducted on an Advanced Triple Junction (ATJ) coupon that was part of a risk reduction effort in the development of a high-powered solar array design by SSL. The ATJ coupon was a small, 4-cell, two-string configuration that has served as the basic test coupon design used in previous SSL environmental aging campaigns. The coupon has many attributes of the flight design; e.g., substrate structure with graphite face sheets, integrated by-pass diodes, cell interconnects, RTV grout, wire routing, etc. The objective of the present test was to evaluate the performance of the coupon after being subjected to induced electrostatic discharge testing at two string voltages (100 V, 150 V) and four array current (1.65 A, 2.0 A, 2.475 A, and 3.3 A). An ESD test circuit, unique to SSL solar array design, was built that simulates the effect of missing cells and strings in a full solar panel with special primary arc flashover circuitry. A total of 73 primary arcs were obtained that included 7 temporary sustained arcs (TSA) events. The durations of the TSAs ranged from 50 micros to 2.9 ms. All TSAs occurred at a string voltage of 150 V. Post-test Large Area Pulsed Solar Simulator (LAPSS), Dark I-V, and By-Pass Diode tests showed that no degradation occurred due to the TSA events. In addition, the post-test insulation resistance measured was > 50 G-ohms between cells and substrate. These test results indicate a robust design for application to a high-current, high-power mission application.

Wright, Kenneth H., Jr.↗

Airplane Capabilities: Translating Non-Normal Information for Operational Decision-Making

We consider how a jet transport airplane interface supports the flight crew in managing airplane system failures (or non-normals) for continued safe flight and landing. The existing state of the art starts with a list of airplane system component failures and asks the flight crew to determine, with the help of non-normal procedures, the operational consequences of those failures. As airplane systems become more complex and interconnected, the flight crew's ability to determine operational consequences will become inadequate. We describe an approach that attempts to translate airplane system failures directly into airplane "capabilities," which is a set of basic airplane functions, such as the ability to stop after landing. This paper describes the overall framework for supporting flight crews in operational decision making and the initial efforts to develop a language and display concepts.

managing airplane system non-normals↗

Personal Computer Monitors Instrumentation Bus

IBM-compatible personal computer used instead of logic analyzer or other special instrument to monitor IEEE-488 interface data bus that interconnects various pieces of laboratory equipment. Needed is short program for computer, commercial general-purpose interface bus circuit card, and adapter cable to link card to bus. Software available in Ada or Quick Basic language.

Conroy, Bruce L.↗

Water system microbial check valve development

Development work on a device for the Space Shuttle that will prevent the transfer of viable microorganisms within water systems is described. The device serves as a check valve in that it prevents the transfer or cross-contamination of microorganisms from a nonpotable system into a potable water system when these systems are interconnected. In this regard, the function of the device is similar to that of the air gap found in conventional one gravity systems. The device is essentially a bed of resin material impregnated with iodine. Basic design data for a variety of flow and temperature conditions are presented, together with results of challenging the beds with suspensions of seven microorganisms including aerobes, anaerobes, and spore formers.

Colombo, G. V.↗

Main memory unit

The development of a main memory unit (MMU) for the space ultrareliable module computer (SUMC) model HTC is discussed. The design, fabrication, and test of basic memory modules (BMM) which were to be used in the design and construction of the MMU are described. The BMM was designed from state-of-the-art technologies which included large scale integration devices mounted and interconnected on a substrate to form a functional module to be utilized in the MMU development. A SUMC memory system design study is discussed which addressed itself to the BMM design and analysis to be conducted to determine the most efficient organization of the BMM in order to establish such modularity features as: word length expandability without redesign, high reliability, and fault tolerance. One MMU was designed, fabricated, tested, and delivered which will be electrical and mechanically compatible with the hybrid technology computer (HTC) model of the SUMC family of computers. The MMU will contain a storage capacity of 8196 36 bit words which includes a parity bit for each 8 bit byte of data.

Source record↗

Application of diffusion bonding to electronic interconnection of flatpack leads

Diffusion-bonded joints between gold-plated Kovar leads and indium-plated copper circuit pads offer some advantages for electronic circuit packaging. Test results show that consistent high strength bonds stronger than the copper circuit foil are achieved by parallel-gap bonding at relatively low power settings. The bonds are basically formed by the alloying of the gold, indium and copper at the bond interface. Other low melting metals such as tin can also be used; however, tin does not offer the ease of bonding that results in consistent separation of the copper foil during pull testing. The investigation was conducted in three parts consisting of: (1) an evaluation of the physical strength of resulting bonds at ambient and elevated temperature, (2) a metallurgical analysis of bonds using scanning electron microscopy and nondispersive X-ray analysis, and (3) evaluation and development of various schemes for multiple lead flatpack bonding.

Korb, R. W.↗

A 100,000 pulse height analyzer for use in High Energy Cosmic Ray Experiments (HECRE) on high altitude balloon flights

A description is given of a wide dynamic range pulse height analyzer system developed for use on High Energy Cosmic Ray Experiment (HECRE) Balloon Flights. A wide dynamic range of 100,000 is obtained by extending the range of a basic 1024 channel analyzer through the use of multiple ranges and range selection. The system described here contains four 100,000 pulse height analyzers. Each 100,000 pulse height analyzer consists of a group of cordwood welded modules mounted and interconnected on a printed circuit card. Four of these card assemblies, the required clock drive circuitry (discrete components mounted and interconnected on a separate card) and three input-output connectors are interconnected and mounted on the system board.

Cancro, C. A.↗

Basic memory module

Construction and electrical characterization of the 4096 x 2-bit Basic Memory Module (BMM) are reported for the Space Ultrareliable Modular Computer (SUMC) program. The module uses four 2K x 1-bit N-channel FET, random access memory chips, called array chips, and two sense amplifier chips, mounted and interconnected on a ceramic substrate. Four 5% tolerance power supplies are required. At the Module, the address, chip select, and array select lines require a 0-8.5 V MOS signal level. The data output, read-strobe, and write-enable lines operate at TTl levels. Although the module is organized as 4096 x 2 bits, it can be used in a 8196 x 1-bit application with appropriate external connections. A 4096 x 1-bit organization can be obtained by depopulating chips.

Tietze, F. C.↗

The motion of interconnected flexible bodies

The equations of motion for an arbitrarily interconnected collection of substructures are derived. The substructures are elastic bodies which may be idealized as finite element assemblies and are subject to small deformations relative to a nominal state. Interconnections between the elastic substructures permit large relative translations and rotations between substructures, governed by Pfaffian constraints describing the connections. Screw connections (permitting rotation about and translation along a single axis) eliminate constraint forces and incorporate modal coupling. The problem of flexible spacecraft simulation is discussed. Hurty's component mode approach is extended by permitting interconnected elastic substructures large motions relative to each other and relative to inertial space. The hybrid coordinate methods are generalized by permitting all substructures to be flexible (rather than only the terminal members of a topological tree of substructures). The basic relationships of continuum mechanics are developed.

Hopkins, A. S.↗

ADAM: An Axisymmetric Duct Aeroacoustic Modeling system

An interconnected system of computer programs for analyzing the propagation and attenuation of sound in aeroengine ducts containing realistic compressible subsonic mean flows, ADAM was developed primarily for research directed towards the reduction of noise emitted from turbofan aircraft engines. The two basic components are a streamtube curvature program for determination of the mean flow, and a finite element code for solution of the acoustic propagation problem. The system, which has been specifically tailored for ease of use, is presently installed at NASA Langley Reseach Center on a Control Data Cyber 175 Computer under the NOS Operating system employing a Tektronix terminal for interactive graphics. The scope and organization of the ADAM system is described. A users guide, examples of input data, and results for selected cases are included.

Abrahamson, A. L.↗

The Electromagnetic Compatibility (EMC) Design Challenge for Scientific Spacecraft Powered by a Stirling Power Converter

A 55 We free-piston Stirling Technology Demonstration Convertor (TDC) has been tested as part of an evaluation to determine its feasibility as a means for significantly reducing the amount of radioactive material required compared to Radioisotope Thermoelectric Generators (RTGs) to support long-term space science missions. Measurements were made to quantify the low frequency magnetic and electric fields radiated from the Stirling's 80 Hertz (Hz) linear alternator and control electronics in order to determine the magnitude of reduction that will be required to protect sensitive field sensors aboard some science missions. One identified "Solar Probe" mission requires a 100 dB reduction in the low frequency magnetic field over typical military standard design limits, to protect its plasma wave sensor. This paper discusses the electromagnetic interference (EMI) control options relative to the physical design impacts for this power system, composed of 3 basic electrical elements. They are (1) the Stirling Power Convertor with its linear alternator, (2) the power switching and control electronics to convert the 90 V, 80 Hz alternator output to DC for the use of the spacecraft, and (3) the interconnecting wiring including any instrumentation to monitor and control items 1 and 2.

Sargent, Noel B.↗

Self-Adaptive System based on Field Programmable Gate Array for Extreme Temperature Electronics

In this work, we report the implementation of a self-adaptive system using a field programmable gate array (FPGA) and data converters. The self-adaptive system can autonomously recover the lost functionality of a reconfigurable analog array (RAA) integrated circuit (IC) [3]. Both the RAA IC and the self-adaptive system are operating in extreme temperatures (from 120 C down to -180 C). The RAA IC consists of reconfigurable analog blocks interconnected by several switches and programmable by bias voltages. It implements filters/amplifiers with bandwidth up to 20 MHz. The self-adaptive system controls the RAA IC and is realized on Commercial-Off-The-Shelf (COTS) parts. It implements a basic compensation algorithm that corrects a RAA IC in less than a few milliseconds. Experimental results for the cold temperature environment (down to -180 C) demonstrate the feasibility of this approach.

adaptive hardwares↗

Block QCA Fault-Tolerant Logic Gates

Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA-based logic gates: One is the need for (and the difficulty of attaining) operation of QCA circuitry at room temperature or, for that matter, at any temperature above a few Kelvins. It has been theorized that room-temperature operation could be made possible by constructing QCA as molecular-scale devices. However, in approaching the lower limit of miniaturization at the molecular level, it becomes increasingly imperative to overcome the second major obstacle, which is the need for (and the difficulty of attaining) high precision in the alignments of adjacent QCA in order to ensure the correct interactions among the quantum dots.

Firjany, Amir↗

Nanoelectronics: Opportunities for future space applications

Further improvements in the performance of integrated electronics will eventually halt due to practical fundamental limits on our ability to downsize transistors and interconnect wiring. Avoiding these limits requires a revolutionary approach to switching device technology and computing architecture. Nanoelectronics, the technology of exploiting physics on the nanometer scale for computation and communication, attempts to avoid conventional limits by developing new approaches to switching, circuitry, and system integration. This presentation overviews the basic principles that operate on the nanometer scale that can be assembled into practical devices and circuits. Quantum resonant tunneling (RT) is used as the center-piece of the overview since RT devices already operate at high temperature (120 degrees C) and can be scaled, in principle, to a few nanometers in semiconductors. Near- and long-term applications of GaAs and silicon quantum devices are suggested for signal and information processing, memory, optoelectronics, and radio frequency (RF) communication.

Frazier, Gary↗