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Digital Application Specific Integrated Circuit Design
Single radiation effects can be transient and static. The charge collected from radiation has a prompt (drift) and a slow (diffusion) component. This current spike causes disparate results: SEU, SET, SEB, MBU, and more. A system level SEE mitigation technique, used to overcome, is the triple module redundancy (TMR). TMR for system Verilog (TMR4SV), written in Python, is the first step towards design IP triplication. It allows various triplication methods for flip flops, clocks, and logic.
Project 21-0041 / ?Strategic Radiation Hardening of Advanced Radio Frequency Integrated Circuits?.
Abstract not provided.
Neutron Displacement Damage in Bipolar Junction Transistors Isolated from an Integrated Circuit
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Modeling Neutron Radiation Damage In Bipolar Junction Transistors Isolated from an Integrated Circuit
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Neural-Inspired Dendritic Multiplication Using a Reconfigurable Analog Integrated Circuit
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Ultra-high Bandwidth, Ultra-high Dynamic Range X-Ray Shock Characterization via Photonic Integrated Circuit
Nuclear weapon component assessment tests at the Z Machine rely on accurate X-ray yield measurements for model validation, design and analysis of component survivability, and source optimization. Yield measurement devices currently used do not provide the requisite certainty to enable accurate and efficient data analysis of test results, which leads to an increase in Z-shots required for evaluation, longer device development times, and higher operation costs. Additionally, current X-ray flux detectors lack high temporal resolution at the tails. Similarly, shock measurement techniques used for component assessment often lack the ability to spatially resolve wave behavior thereby limiting the ability to measure shock propagation dynamics needed to design the next generation of ND components. Here we present the development of a photonic micro-calorimeter and shock sensor consisting of meter-long waveguide spirals that are optomechanically coupled to X-ray absorbing layers to characterize yield and shock propagation at nanosecond timescales.
Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same
An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.
Heterogeneous Integration of 3D Photonic Integrated Circuits.
Abstract not provided.
Integrated circuit authentication from a die material measurement
The various technologies presented herein relate to measuring a signal generated by a die-based test circuit incorporated into an IC and utilizing the measured signal to authenticate the IC. The signal can be based upon a sensor response generated by the test circuit fabricated into the die, wherein the sensor response is based upon a property of the die material. The signal can be compared with a reference value obtained from one or more test circuit(s) respectively located on one or more reference dies, wherein the reference dies are respectively cut from different wafers, and the location at which the reference dies were cut is known. If the measured signal matches the reference value, the die is deemed to be from the same cut location as the dies from which the reference value was obtained. If the measured signal does not match the reference value, the die is not authenticated.
Validating Tools for Detecting Hardware Trojans in Integrated Circuits.
Abstract not provided.
Photonic integrated circuits for generating high-brightness squeezed light
A high-brightness squeezed light source includes a plurality of light squeezing elements and a photonic summing device. The light squeezing elements each output respective squeezed light responsive to receipt of unsqueezed light. The photonic summing device receives the squeezed light output by each of the light squeezing elements and coherently adds the squeezed light to generate a high-brightness squeezed light output. The high-brightness squeezed light output has a greater brightness than the outputs of the light squeezing elements, and a same degree of squeezing as one or more of the outputs of the light squeezing elements.
High-resolution magnetic field fingerprinting of integrated circuit activity with a quantum diamond microscope
Devices for determining a state of a magnetic field-generating article are provided. In various embodiments, a device comprises: a single crystal diamond having a plurality of NV centers, the single crystal diamond configured to be disposed adjacent to a magnetic field-generating article, and configured to generate a fluorescent signal in response to being illuminated by a light source; a coherent light source configured to generate a light beam directed at the single crystal diamond; a microwave (MW) radiation source configured to irradiate the single crystal diamond with a MW signal; a magnetic field source configured to apply a bias magnetic field to the single crystal diamond; a photosensor configured to collect the fluorescent signal generated by the single crystal diamond; and a computing node operatively coupled to each of the coherent light source, the MW radiation source, the magnetic field source, and the photosensor.
Low Cost, High-Throughput, Dense-Fiber Channel Optical Interrogator Based On Photonic Integrated Circuits (PIC) Microchip Technology.
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Delay-resolved spectroscopy in terahertz photonic circuits
Photonic integrated circuits incorporating intersubband transitions are ideal for mid-infrared and terahertz nanophotonics. However, the design of epitaxies has long been inhibited by two factors: the modest predictivity of ab initio theory and the absence of absolute intersubband gain and loss measurements under operating conditions. Existing measurements either yield inaccurate gain profiles or do not accurately assess dependence on frequency, bias, and temperature. Here, we present a delay-resolved absolute-referencing method for accurate gain evaluation without these limitations, addressing a long-standing challenge. By creating a photonic circuit that allows broadband pulses to traverse different lengths of a gain medium, we measure the absolute transmission of intersubband structures. Gain profiles match theoretical predictions at lower temperatures, with gain and dispersion clamping after lasing, and faster-than-expected degradation occurs at higher temperatures. Our approach provides a precise experimental evaluation of temperature-dependent gain performance and gives insight into optimizing temperature performance and frequency comb designs.
On-PIC Light Source Integration & Micro-dispensing of Solder Paste for Flip Chip Application
To reach the next level benefits of photonic integrated circuits (PICs), the Integrated Photonic Systems Roadmap-International describes the necessity of either heterogeneous or hybrid integration of light sources [1]. A new approach for hybrid integration is Photonic Wire Bonding where 3D nanolithography is used to pattern a polymer waveguide that connects light sources to PIC waveguides. The waveguides resemble electrical wire bonds and essentially do the same as their electrical counterpart for packaging photonic chips together. In order to reap the full benefits of a photonic wire bonds, the light source must be carefully packaged. In this work I seek to expand RIT’s photonic packaging capability by establishing a packaging process to integrate light sources, specifically an Indium Phosphide distributed feedback lasers and a reflective semiconductor optical amplifiers, directly onto a photonic integrated circuits. Another necessary requirement for PIC packaging is densely integrated electrical connectivity. In this thesis I developed a fine pitch flip chip interconnect technique demonstrated using gold stud bumps in conjunction with micro-dispensed solder paste. This work opens the door to high density photonic flip chip applications. The micro-dispensed solder paste dots having diameters 50-125 µm are currently being tested at a pitch of 150 µm . The gold stud bumps are formed with 1mil gold wire creating bumps with a diameter of 40-60 µm depending on specific parameter values. These capabilities will allow RIT to assemble and test novel photonic integrated devices, cutting down on the time and cost associated with third party assembly and tests facilities. Thereby keeping RIT at the forefront of photonic research.