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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2017

The Impact of Harness Impedance on Hall Thruster Discharge Oscillations

Hall thrusters exhibit characteristic discharge voltage and current oscillations during steady-state operation. The lower frequency breathing-mode current oscillations are inherent to each thruster and could impact thruster operation and power processing unit (PPU) design. The design of the discharge output filter, in particular, the output capacitor is important because it supplies the high peak current oscillations that the thruster demands. However, space-rated, high-voltage capacitors are not readily available and can have significant mass and volume. So, it is important for a PPU designer to know what is the minimum amount of capacitance required to operate a thruster. Through Simulation Program with Integrated Circuit Emphasis modeling and electrical measurements on the Hall Effect Rocket with Magnetic Shielding thruster, it was shown that the harness impedance between the power supply and the thruster is the main contributor towards generating voltage ripple at the thruster. Also, increasing the size of the discharge filter capacitor, as previously implemented during thruster tests, does not reduce the voltage oscillations. The electrical characteristics of the electrical harness between the discharge supply and the thruster is crucial to system performance and could have a negative impact on performance, life and operation.

hollow cathodes↗
NASA NTRS2017

The Impact of Harness Impedance on Hall Thruster Discharge Oscillations

Hall thrusters exhibit characteristic discharge voltage and current oscillations during steady-state operation. The lower frequency breathing-mode current oscillations are inherent to each thruster and could impact thruster operation and power processing unit (PPU) design. The design of the discharge output filter, in particular, the output capacitor is important because it supplies the high peak current oscillations that the thruster demands. However, space-rated, high-voltage capacitors are not readily available and can have significant mass and volume. So, it is important for a PPU designer to know what is the minimum amount of capacitance required to operate a thruster. Through Simulation Program with Integrated Circuit Emphasis modeling and electrical measurements on the Hall Effect Rocket with Magnetic Shielding thruster, it was shown that the harness impedance between the power supply and the thruster is the main contributor towards generating voltage ripple at the thruster. Also, increasing the size of the discharge filter capacitor, as previously implemented during thruster tests, does not reduce the voltage oscillations. The electrical characteristics of the electrical harness between the discharge supply and the thruster is crucial to system performance and could have a negative impact on performance, life and operation.

ion engines↗
NASA NTRS1983

The physics of a single-event upset in integrated circuits: A review and critique of analytical models for charge collection

When an energetic particle (kinetic energy 0.5 MeV) originating from a radioactive decay or a cosmic ray transverse the active regions of semiconductor devices used in integrated circuit (IC) chips, it leaves along its track a high density electron hole plasma. The subsequent decay of this plasma by drift and diffusion leads to charge collection at the electrodes large enough in most cases to engender a false reading, hence the name single-event upset (SEU). The problem of SEU's is particularly severe within the harsh environment of Jupiter's radiation belts and constitutes therefore a matter of concern for the Galileo mission. The physics of an SEU event is analyzed in some detail. Owing to the predominance of nonlinear space charge effects and the fact that positive (holes) and negative (electrons) charges must be treated on an equal footing, analytical models for the ionized-charge collection and their corresponding currents as a function of time prove to be inadequate even in the simplest case of uniformly doped, abrupt p-n junctions in a one-dimensional geometry. The necessity for full-fledged computer simulation of the pertinent equations governing the electron-hole plasma therefore becomes imperative.

Vonroos, O.↗
NASA NTRS1991

Analysis and characterizations of planar transmission structures and components for superconducting and monolithic integrated circuits

The analysis and modeling of superconducting planar transmission lines were performed. Theoretically, the highest possible Q values of superconducting microstrip line was calculated and, as a result, it provided the Q value that the experiment can aim for. As an effort to search for a proper superconducting transmission line structure, the superconducting microstrip line and coplanar waveguide were compared in terms of loss characteristics and their design aspects. Also, the research was expanded to a superconducting coplanar waveguide family in the microwave packaging environment. Theoretically, it was pointed out that the substrate loss is critical in the superconducting transmission line structures.

Itoh, Tatsuo↗
NASA NTRS1983

Modeling of single-event upset in bipolar integrated circuits

The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

Zoutendyk, J. A.↗
NASA NTRS1993

Predicting Lifetimes Of CMOS ASIC's From Test Data

Concise report discusses recent developments in use of semiempirical mathematical models to predict rates of failure and operating lifetimes of complementary metal oxide/semiconductor (CMOS) application-specific integrated circuits (ASIC's). Each model represents specific mechanism of failure. Once failure mechanisms and models relevant to given ASIC chosen, adjustable parameters in models fitted to life-test data acquired from representative integrated-circuit structures on test coupons fabricated along with ASIC's. Then design parameters of ASIC's incorporated into models, and models yield lifetimes.

Buehler, Martin G.↗
NASA NTRS1988

Simulation of proton-induced energy deposition in integrated circuits

A time-efficient simulation technique was developed for modeling the energy deposition by incident protons in modern integrated circuits. To avoid the excessive computer time required by many proton-effects simulators, a stochastic method was chosen to model the various physical effects responsible for energy deposition by incident protons. Using probability density functions to describe the nuclear reactions responsible for most proton-induced memory upsets, the simulator determines the probability of a proton hit depositing the energy necessary for circuit destabilization. This factor is combined with various circuit parameters to determine the expected error-rate in a given proton environment. An analysis of transient or dose-rate effects is also performed. A comparison to experimental energy-disposition data proves the simulator to be quite accurate for predicting the expected number of events in certain integrated circuits.

Fernald, Kenneth W.↗
NASA NTRS1986

Empirical modeling of Single-Event Upset (SEU) in NMOS depletion-mode-load static RAM (SRAM) chips

A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.

Zoutendyk, J. A.↗
NASA NTRS1985

Single-Event Upset (SEU) model verification and threshold determination using heavy ions in a bipolar static RAM

Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and O ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device. The threshold for onset of SEU has been observed by the variation of energy, ion species and angle of incidence. The results obtained from the computer circuit-simulation modeling and experimental model verification demonstrate a viable methodology for modeling SEU in bipolar integrated circuits.

Zoutendyk, J. A.↗
NASA NTRS2017

SPICE Modeling of Body Bias Effect in 4H-SiC Integrated Circuit Resistors

The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

Neudeck, Philip G.↗
NASA NTRS2016

First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 C to 500 C SPICE simulation models of first order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

JFET↗
DOE OSTI2020

Circuit Modelling of the Mechanical-Motion-Rectifier for Electrical Simulation of Ocean Wave Power Take-off

As is the case with several other mechanical power takeoffs (PTOs), the mechanical-motion-rectifier (MMR) based PTO consists of components such as one-way clutches, gears, a ball screw, mechanical couplings, and a generator. Equivalent circuit models have been created in this paper to describe the dry frictions, viscous damping, and mechanical compliances in these components, so the non-ideal efficiency and nonlinear force of the PTO can be predicted in electrical simulations by integrating these sub-circuit models. The circuit model is simplified, and its parameters are categorized as dc and ac unknowns. The dc and ac tests on the PTO are performed sequentially to extract two sets of parameters through linear regression or nonlinear curve fitting. Then, the model is validated through its prediction capability over 25 test conditions on input forces, output voltages, and efficiencies, with correlation coefficients of 0.9, 0.98, and 0.981, respectively.

42 ENGINEERING↗
NASA NTRS1986

Simulating Single-Event Upsets in Bipolar RAM's

Simulation technique saves testing. Uses interactive version of SPICE (Simulation Program with Integrated Circuit Emphasis). Device and subcircuit models available in software used to construct macromodel for an integrated bipolar transistor. Time-dependent current generators placed inside transistor macromodel to simulate charge collection from ion track. Significant finding of experiments is standard design practice of reducing power in unaddressed bipolar RAM cell increases sensitivity of cell to single-event upsets.

Zoutendyk, J. A.↗
NASA NTRS2021

Constrained Inversion of a Microwave Snowpack Emission Model Using Dictionary Matching: Applications for GPM Satellite

This article presents a new algorithmic framework for multilayer inversion of the dense media radiative transfer (DMRT) equations of snowpack emission, with particular emphasis on the role of high-frequency microwave channels above 60 GHz. The approach relies on dictionary matching and locally constrained least squares. The results demonstrate that the algorithm can invert the DMRT model and retrieve depth, density, and grain size of a single-layer snowpack when dependencies of density and grain size on depth are properly accounted for. However, as the number of layers increases, the sensitivity of the inversion to observation noise grows markedly. Using observations, over the Great Plains in the United States, from the microwave imager onboard the global precipitation measurement (GPM, 10-166 GHz) core satellite, the initial results demonstrate that under a clear-sky condition and no vegetation canopy, the algorithm is capable to retrieve the snow depth and water equivalent of seasonal snow with a mean absolute error (MAE) of less than 0.15 m--when compared to the high-resolution analysis data from the SNOw Data Assimilation System (SNODAS).

Snow↗