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All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Phase-shifted Bragg gratings in a foundry silicon nitride platform

Bragg gratings are key optical elements for applications in communications, sensing, and lasers. Phase-shifted Bragg gratings are a special case where the simple periodic structure is altered to allow a narrow spectral passband within the optical bandgap. Here, we demonstrate phase-shifted silicon nitride gratings fabricated using 193 nm deep ultraviolet lithography (DUV) on the AIM Photonics 300 mm silicon photonics foundry line. We measure the grating properties and verify the results with a transfer-matrix method (TMM) model. The standard grating expressions for extracting the coupling coefficient κ and bandwidth do not apply and are updated to account for the phase shift. These results inform future designs for on-chip grating filters and distributed feedback (DFB) lasers.

Husko, Chad (ORCID:0000000271252518)↗
DOE OSTI2023

Integrated photonic molecule Brillouin laser with a high-power sub-100-mHz fundamental linewidth

Photonic integrated lasers with an ultra-low fundamental linewidth and a high output power are important for precision atomic and quantum applications, high-capacity communications, and fiber sensing, yet wafer-scale solutions have remained elusive. Here we report an integrated stimulated Brillouin laser (SBL), based on a photonic molecule coupled resonator design, that achieves a sub-100-mHz fundamental linewidth with greater than 10-mW output power in the C band, fabricated on a 200-mm silicon nitride (Si 3 N 4 ) CMOS-foundry compatible wafer-scale platform. The photonic molecule design is used to suppress the second-order Stokes (S2) emission, allowing the primary lasing mode to increase with the pump power without phase noise feedback from higher Stokes orders. The nested waveguide resonators have a 184 million intrinsic and 92 million loaded Q, over an order of magnitude improvement over prior photonic molecules, enabling precision resonance splitting of 198 MHz at the S2 frequency. We demonstrate S2-suppressed single-mode SBL with a minimum fundamental linewidth of 71±18 mHz, corresponding to a 23±6-mHz 2 /Hz white-frequency-noise floor, over an order of magnitude lower than prior integrated SBLs, with an ∼11-mW output power and 2.3-mW threshold power. The frequency noise reaches the resonator-intrinsic thermo-refractive noise from 2-kHz to 1-MHz offset. The laser phase noise reaches −155 dBc/Hz at 10-MHz offset. The performance of this chip-scale SBL shows promise not only to improve the reliability and reduce size and cost but also to enable new precision experiments that require the high-speed manipulation, control, and interrogation of atoms and qubits. Realization in the silicon nitride ultra-low loss platform is adaptable to a wide range of wavelengths from the visible to infrared and enables integration with other components for systems-on-chip solutions for a wide range of precision scientific and engineering applications including quantum sensing, gravitometers, atom interferometers, precision metrology, optical atomic clocks, and ultra-low noise microwave generation.

Liu, Kaikai (ORCID:0000000213609646)↗
NASA NTRS1993

NASA Space Engineering Research Center for VLSI System Design

This annual report outlines the activities of the past year at the NASA SERC on VLSI Design. Highlights for this year include the following: a significant breakthrough was achieved in utilizing commercial IC foundries for producing flight electronics; the first two flight qualified chips were designed, fabricated, and tested and are now being delivered into NASA flight systems; and a new technology transfer mechanism has been established to transfer VLSI advances into NASA and commercial systems.

Source record↗
NASA NTRS2005

Improvements in Fabrication of Sand/Binder Cores for Casting

Three improvements have been devised for the cold-box process, which is a special molding process used to make sand/binder cores for casting hollow metal parts. These improvements are: The use of fiber-reinforced composite binder materials (in contradistinction to the non-fiber-reinforced binders used heretofore), The substitution of a directed-vortex core-blowing subprocess for a prior core-blowing process that involved a movable gassing plate, and The use of filters made from filtration-grade fabrics to prevent clogging of vents. For reasons that exceed the scope of this article, most foundries have adopted the cold-box process for making cores for casting metals. However, this process is not widely known outside the metal-casting industry; therefore, a description of pertinent aspects of the cold-box process is prerequisite to a meaningful description of the aforementioned improvements. In the cold-box process as practiced heretofore, sand is first mixed with a phenolic resin (considered to be part 1 of a three-part binder) and an isocyanate resin (part 2 of the binder). Then by use of compressed air, the mixture is blown into a core box, which is a mold for forming the core. Next, an amine gas (part 3 of the binder) that acts as a catalyst for polymerization of parts 1 and 2 is blown through the core box. Alternatively, a liquid amine that vaporizes during polymerization can be incorporated into the sand/resin mixture. Once polymerization is complete, the amine gas is purged from the core box by use of compressed air. The finished core is then removed from the core box.

Bakhitiyarov, Sayavur I.↗
DOE OSTI2026

Deriving effective electrode–ion interactions from free-energy profiles at electrochemical interfaces

Understanding ion adsorption at electrified metal–electrolyte interfaces is essential for accurate modeling of electrochemical systems. Here, in this study, we systematically investigate the free energy profiles of Na + , Cl − , and F − ions at the Au(111)–water interface using enhanced sampling molecular dynamics with both classical force fields and machine-learned interatomic potentials (MLIPs). Our classical metadynamics results reveal a strong dependence of predicted ion adsorption on the Lennard-Jones parameters, highlighting that—without due care—standard mixing rules can lead to qualitatively incorrect descriptions of ion–metal interactions. We present a systematic methodology for tuning the cross term LJ parameters to control adsorption energetics in agreement with more accurate models. As a surrogate for an ab initio model, we employed the recently released Universal Models for Atoms MLIP, which validates classical trends and displays strong specific adsorption for chloride, weak adsorption for fluoride, and no specific adsorption for sodium, in agreement with experimental and theoretical expectations. By integrating molecular-level adsorption free energies into continuum models of the electric double layer, we show that specific ion adsorption substantially alters the interfacial ion population, the potential of zero charge, and the differential capacitance of the system. Our results underscore the critical importance of force field parameterization and advanced interatomic potentials for the predictive modeling of ion-specific effects at electrified interfaces and provide a robust framework for bridging molecular simulations and continuum electrochemical models.

Roncoroni, Fabrice [Lawrence Berkeley National Lab↗
NASA NTRS2023

Processing Choices for Achieving Long Term IC Operation at 500° C

The prospects for beneficial infusion of integrated circuits (ICs) into previously inaccessible extreme-temperature application environments has increased with recent NASA Glenn demonstrations of 4H-SiC Junction Field Effect Transistor & Resistor (JFET-R) chips functioning for over a year at 500 °C in air ambient [1]. This paper focuses on fabrication process choices believed key to demonstrated 500 °C durability that must be considered when porting this uniquely durable IC capability into commercial foundry manufacturing.

SiC, JFET, Integrated Circuits, High-Temperature, ↗
NASA NTRSDate not supplied

Processing Choices for Achieving Long Term IC Operation at 500 °C

The prospects for beneficial infusion of integrated circuits (ICs) into previously inaccessible extreme-temperature application environments has increased with recent NASA Glenn demonstrations of 4H-SiC Junction Field Effect Transistor & Resistor (JFET-R) chips functioning for over a year at 500 °C in air ambient. This paper focuses on fabrication process choices believed key to demonstrated 500 °C durability that must be considered when porting this uniquely durable IC capability into commercial foundry manufacturing.

silicon carbide↗
NASA NTRS2005

Improved Method of Manufacturing SiC Devices

The phrase, "common-layered architecture for semiconductor silicon carbide" ("CLASSiC") denotes a method of batch fabrication of microelectromechanical and semiconductor devices from bulk silicon carbide. CLASSiC is the latest in a series of related methods developed in recent years in continuing efforts to standardize SiC-fabrication processes. CLASSiC encompasses both institutional and technological innovations that can be exploited separately or in combination to make the manufacture of SiC devices more economical. Examples of such devices are piezoresistive pressure sensors, strain gauges, vibration sensors, and turbulence-intensity sensors for use in harsh environments (e.g., high-temperature, high-pressure, corrosive atmospheres). The institutional innovation is to manufacture devices for different customers (individuals, companies, and/or other entities) simultaneously in the same batch. This innovation is based on utilization of the capability for fabrication, on the same substrate, of multiple SiC devices having different functionalities (see figure). Multiple customers can purchase shares of the area on the same substrate, each customer s share being apportioned according to the customer s production-volume requirement. This makes it possible for multiple customers to share costs in a common foundry, so that the capital equipment cost per customer in the inherently low-volume SiC-product market can be reduced significantly. One of the technological innovations is a five-mask process that is based on an established set of process design rules. The rules provide for standardization of the fabrication process, yet are flexible enough to enable multiple customers to lay out masks for their portions of the SiC substrate to provide for simultaneous batch fabrication of their various devices. In a related prior method, denoted multi-user fabrication in silicon carbide (MUSiC), the fabrication process is based largely on surface micromachining of poly SiC. However, in MUSiC one cannot exploit the superior sensing, thermomechanical, and electrical properties of single-crystal 6H-SiC or 4H-SiC. As a complement to MUSiC, the CLASSiC five-mask process can be utilized to fabricate multiple devices in bulk single-crystal SiC of any polytype. The five-mask process makes fabrication less complex because it eliminates the need for large-area deposition and removal of sacrificial material. Other innovations in CLASSiC pertain to selective etching of indium tin oxide and aluminum in connection with multilayer metallization. One major characteristic of bulk micromachined microelectromechanical devices is the presence of three-dimensional (3D) structures. Any 3D recesses that already exist at a given step in a fabrication process usually make it difficult to apply a planar coat of photoresist for metallization and other subsequent process steps. To overcome this difficulty, the CLASSiC process includes a reversal of part of the conventional flow: Metallization is performed before the recesses are etched.

Okojie, Robert S.↗
NASA NTRS2011

Nanoscale Deformable Optics

Several missions and instruments in the conceptual design phase rely on the technique of interferometry to create detectable fringe patterns. The intimate emplacement of reflective material upon electron device cells based upon chalcogenide material technology permits high-speed, predictable deformation of the reflective surface to a subnanometer or finer resolution with a very high degree of accuracy. In this innovation, a layer of reflective material is deposited upon a wafer containing (perhaps in the millions) chalcogenic memory cells with the reflective material becoming the front surface of a mirror and the chalcogenic material becoming a means of selectively deforming the mirror by the application of heat to the chalcogenic material. By doing so, the mirror surface can deform anywhere from nil to nanometers in spots the size of a modern day memory cell, thereby permitting realtime tuning of mirror focus and reflectivity to mitigate aberrations caused elsewhere in the optical system. Modern foundry methods permit the design and manufacture of individual memory cells having an area of or equal to the Feature (F) size of the design (assume 65 nm). Fabrication rules and restraints generally require the instantiation of one memory cell to another no closer than 1.5 F, or, for this innovation, 90 nm from its neighbor in any direction. Chalcogenide is a semiconducting glass compound consisting of a combination of chalcogen ions, the ratios of which vary according to properties desired. It has been shown that the application of heat to cells of chalcogenic material cause a large alteration in resistance to the range of 4 orders of magnitude. It is this effect upon which chalcogenidebased commercial memories rely. Upon removal of the heat source, the chalcogenide rapidly cools and remains frozen in the excited state. It has also been shown that the chalcogenide expands in volume because of the applied heat, meaning that the coefficient of expansion of chalcogenic materials is larger than 1. In this innovation, chalcogenidebased cells are addressed (as though they are a memory), and heated and cooled according to well-established criteria. In doing so, the exact size of chalcogenide cell deformation is known and predictable; therefore, the deformation of the reflective surface is, likewise, known and predictable. Control electronics can also be implemented so that a closed-loop feedback can be maintained. Changing the contents of the chalcogenide memory cells can compensate for any change in environmental effects that might cause a change in optical path. This real-time control provides significant control and stability in use conditions.

Strauss, Karl F.↗
DOE OSTI2022

Ultra-low loss visible light waveguides for integrated atomic, molecular, and quantum photonics

Atomic, molecular and optical (AMO) visible light systems are the heart of precision applications including quantum, atomic clocks and precision metrology. As these systems scale in terms of number of lasers, wavelengths, and optical components, their reliability, space occupied, and power consumption will push the limits of using traditional laboratory-scale lasers and optics. Visible light photonic integration is critical to advancing AMO based sciences and applications, yet key performance aspects remain to be addressed, most notably waveguide losses and laser phase noise and stability. Additionally, a visible light integrated solution needs to be wafer-scale CMOS compatible and capable of supporting a wide array of photonic components. While the regime of ultra-low loss has been achieved at telecommunication wavelengths, progress at visible wavelengths has been limited. Here, we report the lowest waveguide losses and highest resonator Qs to date in the visible range, to the best of our knowledge. We report waveguide losses at wavelengths associated with strontium transitions in the 461 nm to 802 nm wavelength range, of 0.01 dB/cm to 0.09 dB/cm and associated intrinsic resonator Q of 60 Million to 9.5 Million, a decrease in loss by factors of 6x to 2x and increase in Q by factors of 10x to 1.5x over this visible wavelength range. Additionally, we measure an absorption limited loss and Q of 0.17 dB/m and 340 million at 674 nm. This level of performance is achieved in a wafer-scale foundry compatible Si 3 N 4 platform with a 20 nm thick core and TEOS-PECVD deposited upper cladding oxide, and enables waveguides for different wavelengths to be fabricated on the same wafer with mask-only changes per wavelength. These results represent a significant step forward in waveguide platforms that operate in the visible, opening up a wide range of integrated applications that utilize atoms, ions and molecules including sensing, navigation, metrology and clocks.

Chauhan, Nitesh↗
NASA NTRSDate not supplied

Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments

This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient, 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, a majority of processing steps to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment.

high temperature↗
DOE OSTI2023

20 kV Gallium Nitride pn Diode Electro-Magnetic Pulse Arrestor for Grid Reliability (Final Scientific/Technical Report)

This project developed vertical Gallium Nitride (GaN) pn diodes under two main thrusts: (1) A focus on relatively higher-voltage devices for use as fast EMP arrestors to protect the electric grid; and (2) A focus on a Foundry effort to establish the manufacturability of relatively lower voltage devices. For the first thrust, the aim was to develop devices that go into avalanche breakdown to clamp the voltage across sensitive grid equipment subject to voltage transients induced by electromagnetic pulses (EMPs). Devices with breakdown voltages exceeding 6.5 kV were achieved, and breakdown times shorter than 1 ns were demonstrated, which is sufficiently fast to protect against the fast component of an EMP-induced signal. Key challenges included the epitaxial growth of thick (50 µm or more), low-doped (low 10 15 cm -3 range) GaN layers comprising the drift regions of the diodes, as well as the design and fabrication of edge termination structures (step-etched junction termination extensions) to prevent premature breakdown. Midway through the project, an additional emphasis was put on large-area, high-current devices, and forward currents of approximately 400 A were achieved in composite devices towards the end of the project. Experimental and theoretical studies of impact ionization and avalanche ruggedness were also conducted. For the second thrust (the Foundry), the focus was primarily on 1.2-kV-class devices, although towards the end of the project outstanding results on 3.3-kV class devices were also achieved. The aim of the Foundry was to develop a high-yield, reliable, and economic vertical GaN pn diode process. The Foundry conducted characterization of incoming epitaxial material and correlated this information with the yield and performance of fully processed devices. Wafer maps of diode characteristics such as forward and reverse current as well as capacitance-voltage curves were measured using auto-probing. Several mask sets comprising different-area devices as well as multiple edge termination designs (implanted junction termination extensions, guard rings, and combinations thereof) were studied, and machine-learning-based approaches were utilized to analyze the data. Packaging and reliability efforts were also undertaken for the Foundry diodes, which are necessary for a viable commercial process.

20KV↗
DOE OSTI2023

20 kV Gallium Nitride pn Diode Electro-Magnetic Pulse Arrestor for Grid Reliability (Final Report)

This project developed vertical Gallium Nitride (GaN) pn diodes under two main thrusts: (1) A focus on relatively higher-voltage devices for use as fast EMP arrestors to protect the electric grid; and (2) A focus on a Foundry effort to establish the manufacturability of relatively lower-voltage devices. For the first thrust, the aim was to develop devices that go into avalanche breakdown to clamp the voltage across sensitive grid equipment subject to voltage transients induced by electromagnetic pulses (EMPs). Devices with breakdown voltages exceeding 6.5 kV were achieved, and breakdown times shorter than 1 ns were demonstrated, which is sufficiently fast to protect against the fast component of an EMP-induced signal. Key challenges included the epitaxial growth of thick (50 um or more), low-doped (low 10 15 cm -3 range) GaN layers comprising the drift regions of the diodes, as well as the design and fabrication of edge termination structures (step-etched junction termination extensions) to prevent premature breakdown. Midway through the project, an additional emphasis was put on large-area, high-current devices, and forward currents of approximately 400 A were achieved in composite devices towards the end of the project. Experimental and theoretical studies of impact ionization and avalanche ruggedness were also conducted. For the second thrust (the Foundry), the focus was primarily on 1.2-kV-class devices, although towards the end of the project outstanding results on 3.3-kV-class devices were also achieved. The aim of the Foundry was to develop a high-yield, reliable, and economic vertical GaN pn diode process. The Foundry conducted characterization of incoming epitaxial material and correlated this information with the yield and performance of fully processed devices. Wafer maps of diode characteristics such as forward and reverse current as well as capacitance-voltage curves were measured using auto-probing. Several mask sets comprising different-area devices as well as multiple edge termination designs (implanted junction termination extensions, guard rings, and combinations thereof) were studied, and machine-learning-based approaches were utilized to analyze the data. Packaging and reliability efforts were also undertaken for the Foundry diodes, which are necessary for a viable commercial process.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2025

Fabrication and Testing of Solid-Solution Strengthened Corrosion Resistant Alloys For Service in Molten Fluoride Environments

The demand for higher system thermal efficiencies requires the operation of power generation cycles and heat conversion systems at progressively higher temperatures. As the system operating temperature increases, existing materials may not provide adequate mechanical properties or environmental compatibility or both. There is an increasing commercial interest in the development and deployment of liquid-fueled Molten Salt Reactors (MSRs). Hastelloy®N, the highest performing candidate MSR structural alloy, is not capable of operations at temperatures above 700°C, thus limiting the performance of these systems. Using an Integrated Computational Materials Engineering (ICME)-approach and small laboratory scale heats, ORNL developed a class of patented alloys covered by U.S. Patent 9, 435, 011 B2, “Creep-resistant, Cobalt-free alloys for high temperature, liquid-salt heat exchanger systems,” similar to Hastelloy®N in that they are primarily solid solution strengthened. In contrast to precipitation strengthened alloys, the microstructure of solid solution alloys and hence the high temperature mechanical properties are stable for extended periods of time allowing long reactor operating life. The new alloys have shown to possess good resistance to liquid fluorides at temperatures up to 850°C and have significantly improved creep properties when compared to Hastelloy®N. The purpose of the CRADA project was for ORNL to collaborate with Haynes International- a materials producer, MetalTek International- a foundry, and Kairos Power – an advanced reactor developer – to scale-up selected alloys, evaluate their properties, and identify one solid solution strengthened alloy that can meet the property requirements for the reactor being developed by Kairos Power and other similar liquid fluoride-salt cooled reactors. As part of the project, eight alloys were down-selected and fabricated in larger industrial scale heats by Haynes International. Resistance to molten salt was evaluated in flowing FLiNaK and FLiBe by Kairos Power using their Rotating Cage Loop (RCL) system. Accounting for iron deposition during these tests, the new alloys displayed very low net mass change showing excellent corrosion performance in molten salt. Creep properties evaluated at ORNL were found to be better than that of Hastelloy®N and 316 stainless steel. Long-term stabilities of the alloys evaluated by Haynes International showed that these alloys have excellent thermal stability in the temperature range 704.4-815.6°C, with the change in strength and ductility being less than 10-15% after a 4000-hour exposure at 815.6°C. Autogenously Gas Tungsten Arc Welding (GTAW) welded samples showed less than 10% change in yield strength / ultimate tensile strength / total elongation compared to the basemetal, indicating that the alloys have excellent weldability. Three parts were successfully investment-cast using one alloy with very little voiding showing feasibility of fabricating parts using the casting process. This project enabled extensive interaction between the material producer Haynes International, casting supplier MetalTek, and reactor developer Kairos Power. This facilitated testing of materials and components produced using the newly developed alloys by the end-user. This allowed the generation of critical dataset required for down-selection of a few promising alloys for further development. This data is also currently being shared with other reactor designers for them to evaluate the suitability of this alloy for their reactor design. The availability of this alloy will ultimately enable the design and development and deployment of MSRs with increased temperature of operation and thus, improved efficiencies.

99 GENERAL AND MISCELLANEOUS↗
DOE OSTI2025

Fabrication and Testing of Solid-Solution Strengthened Corrosion Resistant Alloys For Service in Molten Fluoride Environments

The demand for higher system thermal efficiencies requires the operation of power generation cycles and heat conversion systems at progressively higher temperatures. As the system operating temperature increases, existing materials may not provide adequate mechanical properties or environmental compatibility or both. There is an increasing commercial interest in the development and deployment of liquid-fueled Molten Salt Reactors (MSRs). Hastelloy®N, the highest performing candidate MSR structural alloy, is not capable of operations at temperatures above 700°C, thus limiting the performance of these systems. Using an Integrated Computational Materials Engineering (ICME)-approach and small laboratory scale heats, ORNL developed a class of patented alloys covered by U.S. Patent 9,435,011 B2, “Creep-resistant, Cobalt-free alloys for high temperature, liquid-salt heat exchanger systems,” similar to Hastelloy®N in that they are primarily solid solution strengthened. In contrast to precipitation strengthened alloys, the microstructure of solid solution alloys and hence the high temperature mechanical properties are stable for extended periods of time allowing long reactor operating life. The new alloys have shown to possess good resistance to liquid fluorides at temperatures up to 850°C and have significantly improved creep properties when compared to Hastelloy®N. The purpose of the CRADA project was for ORNL to collaborate with Haynes International- a materials producer, MetalTek International- a foundry, and Kairos Power – an advanced reactor developer – to scale-up selected alloys, evaluate their properties, and identify one solid solution strengthened alloy that can meet the property requirements for the reactor being developed by Kairos Power and other similar liquid fluoride-salt cooled reactors. As part of the project, eight alloys were down-selected and fabricated in larger industrial scale heats by Haynes International. Resistance to molten salt was evaluated in flowing FLiNaK and FLiBe by Kairos Power using their Rotating Cage Loop (RCL) system. Accounting for iron deposition during these tests, the new alloys displayed very low net mass change showing excellent corrosion performance in molten salt. Creep properties evaluated at ORNL were found to be better than that of Hastelloy®N and 316 stainless steel. Long-term stabilities of the alloys evaluated by Haynes International showed that these alloys have excellent thermal stability in the temperature range 704.4-815.6°C, with the change in strength and ductility being less than 10-15% after a 4000-hour exposure at 815.6°C. Autogenously Gas Tungsten Arc Welding (GTAW) welded samples showed less than 10% change in yield strength / ultimate tensile strength / total elongation compared to the basemetal, indicating that the alloys have excellent weldability. Three parts were successfully investment-cast using one alloy with very little voiding showing feasibility of fabricating parts using the casting process. This project enabled extensive interaction between the material producer Haynes International, casting supplier MetalTek, and reactor developer Kairos Power. This facilitated testing of materials and components produced using the newly developed alloys by the end-user. This allowed the generation of critical dataset required for down-selection of a few promising alloys for further development. This data is also currently being shared with other reactor designers for them to evaluate the suitability of this alloy for their reactor design. The availability of this alloy will ultimately enable the design and development and deployment of MSRs with increased temperature of operation and thus, improved efficiencies.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Scalable free-space photonic antennas in foundry SOI silicon photonic platforms

We present a flexible, scalable, and low-noise design scheme for coupling free-space light into a silicon-on-insulator (SOI) electronic-photonic integrated circuit. The proposed scheme utilizes arrays of grating couplers with compact, inverse-designed power combining networks to couple a distributed optical collection area to a single output waveguide, forming a photonic antenna. Fabrication density compliance is maintained regardless of the antenna size, and the collection area can be scaled while maintaining a fixed noise floor. Using experimental grating array antennas fabricated in the GF45CLO platform, we demonstrate up to a 6.7× increase in the signal-to-noise ratio (SNR) of a lens-less monolithic free-space photonic receiver using a 4×4 grating array.

Rollinson, John (ORCID:0000000157130832)↗
NASA NTRS1986

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

Olson, E. M.↗
DOE OSTI2024

Systematic improvements in transmon qubit coherence enabled by niobium surface encapsulation

Abstract We present a transmon qubit fabrication technique that yields systematic improvements in T 1 relaxation times. We encapsulate the surface of niobium and prevent the formation of its lossy surface oxide. By maintaining the same superconducting metal and only varying the surface, this comparative investigation examining different capping materials, such as tantalum, aluminum, titanium nitride, and gold, as well as substrates across different qubit foundries demonstrates the detrimental impact that niobium oxides have on coherence times of superconducting qubits, compared to native oxides of tantalum, aluminum or titanium nitride. Our surface-encapsulated niobium qubit devices exhibit T 1 relaxation times 2–5 times longer than baseline qubit devices with native niobium oxides. When capping niobium with tantalum, we obtain median qubit lifetimes above 300 μs, with maximum values up to 600 μs. Our comparative structural and chemical analysis provides insight into why amorphous niobium oxides may induce higher losses compared to other amorphous oxides.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗