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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

A PIPS + SrI 2 (Eu) detector for atmospheric radioxenon monitoring

The PIPS–SrI 2 (Eu) is a prototype atmospheric radioxenon detection system designed at Oregon State University in support of international efforts towards monitoring clandestine nuclear weapon testing activities. This detector aims to address some shortcomings found in currently deployed beta–gamma atmospheric radioxenon detection systems, such as lackluster energy resolution and memory effect, by employing modern detection materials and readout. The system uses a PIPSBox, a silicon-based gas cell, for electron detection, and a pair of ultrabright, D-shaped SrI 2 (Eu) scintillators coupled to silicon photomultipliers for photon detection. A custom eight-channel digital pulse processor equipped with a field programmable gate-array (FPGA) identifies electron–photon coincidences between the volumes in near real-time. Gas samples of the four radioxenon isotopes of interest were independently measured with the PIPS–SrI 2 (Eu) detection system to determine energy resolution and efficiency. Application of FPGA-based coincidence discrimination in near real-time reduced the ambient background count rate by 95.85 ± 0.04%. Using parameters from the Xenon International gas processing unit and assuming a blank sample and zero memory effect the minimum detectable concentrations (MDCs) for the isotopes were calculated to be 0.12 ± 0.03, 0.27 ± 0.05, 0.15 ± 0.02, and 1.00 ± 0.08 mBq/m 3 air for 131m Xe, 133 Xe, 133m Xe, and 135 Xe, respectively. These MDC estimates compare well with other radioxenon detection systems employed in the International Monitoring System (IMS) and indicate that the PIPS–SrI 2 (Eu) is in compliance with the Comprehensive Nuclear Test-Ban-Treaty Organization (CTBTO) sensitivity requirement of ≤ 1 mBq/m 3 for 133 Xe.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Initial assessment of second generation of large-area picosecond photodetectors with multi-channel systems-on-a-chip readout

Here, we first briefly describe the history and motivation behind Cherenkov and scintillation light detection. We then discuss the instrumentation needed to detect these photons as it applies to both photodetectors and readout electronics. One of the motivations is future large neutrino detectors that could, in principle, differentiate between Cherenkov and scintillation light if using novel water-based scintillators. In this paper, we present the first measurements utilizing the second generation of Large Area Picosecond Photodetectors (LAPPDs) in conjunction with commercial system-on-a-chip readouts from Nalu Scientific—in particular, the High Density System on Chip (HDSoC) and Advanced ASoC Rapid Digitizer, Variable Adaptive Readout Chip (AARDVARC) platforms. These state-of-the-art full-waveform digitizers feature sampling rates on the order of 1 and 10 samples per nanosecond, respectively. Using a picosecond laser, we measured the timing jitter between a pair of LAPPD channels, demonstrating the potential of this setup for precise timing applications.

Li, V. A. [Lawrence Livermore National Laboratory ↗
DOE OSTI2026

Design and Modeling of the Charge Readout of a SiMOS Quantum Dot with a Single Electron Transistor and CryoCMOS

Single electron spin qubits trapped in SiMOS quantum dots are a promising technology for scaling to thousand- or million-qubit systems due to their compatibility with mature CMOS manufacturing processes. A readout system that combines a single electron transistor with a custom cryogenic CMOS amplification and digitization chain offers key advantages by avoiding the use of bulky RF components or room-temperature interconnects. We present design techniques and simulation results for an optimized qubit-SET cryoCMOS interface, culminating in the design of the QNDR1 ASIC, the first cryogenic readout ASIC designed under the Quandarum project, which targets the development of a many-channel spin qubit based detector for use in high energy physics.

Quinn, Adam [Fermilab] (ORCID:0009000605056371)↗
DOE OSTI2026

Readout Noise of Digital Frequency Multiplexed TES Detectors for CUPID

The superconducting transition-edge sensor (TES) detectors have been the standard in cosmic microwave background (CMB) experiments for almost two decades and are now being adapted for use in nuclear physics, such as neutrinoless double beta decay searches. In this article, we focus on a new high-bandwidth frequency multiplexed TES readout system developed for CUPID, a neutrinoless double beta decay experiment that will replace CUORE. In order to achieve the high energy resolution requirements for CUPID, the readout noise of the system must be kept to a minimum. Low TES operating resistance and long wiring between the readout SQUID and the warm electronics are needed for CUPID, prompting a careful consideration of the design parameters of this application of frequency multiplexing. In this work, we characterize the readout noise of the newly designed frequency multiplexed TES readout system for CUPID and construct a noise model to understand it. Here, we find that current sharing between the SQUID coil impedance and other branches of the circuit, as well as the long output wiring, worsen the readout noise of the system. To meet noise requirements, a SQUID with a low input inductance, high transimpedance, and/or low dynamic impedance is needed, and the wiring capacitance should be kept as small as possible. Alternatively, the option of adding a cryogenic low-noise amplifier at the output of the SQUID should be explored.

CUPID↗
DOE OSTI2024

The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results

Exploiting the “sparse” nature of the information in XPCS (X-ray Photon Correlation Spectroscopy) and XSVS (Speckle Visibility Spectroscopy) experiments, we present the SparkPix-S, a 3-sides buttable Application Specific Integrated Circuit (ASIC) based on a sparsified readout strategy for large-format hybrid detectors. The SparkPix-S architecture, based on the successful ePix family, will be composed as follows: a front-end 2-D matrix of 384×352 square pixels with 50 µm pitch is arranged to match the dimensions of a PIN Si-sensor matrix; charge readout, signal shaping and amplitude discrimination is performed at pixel-level, by means of a low-power (<18 µW) analog processor, which, in case of an event, negotiates access to an analog bus placed every other column; on the chip periphery (balcony), the information on each bus is digitized by an array of successive approximation analog-to-digital converters (SAR-ADCs) running at 10 Msps; on the digital back-end the global logic will generate the output data stream using low-voltage differential signalling (LVDS). A first prototype of the SparkPix-S, with a reduced matrix size of 96×96 pixels, is currently under production on a 130 nm CMOS technology. Simulated performance results show an equivalent noise charge <60 el. r.m.s. at 1 MHz repetition rate, with a maximum input energy of 60 keV and capability to discriminate charge signals with equivalent energy as low as 900 eV.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

Characterization of high-flux cadmium zinc telluride detectors coupled to MM-PAD readout ASICs for high-flux X-ray applications

High-flux cadmium zinc telluride (HF-CZT) is a promising material for next-generation X-ray imaging due to its high stopping power, wide bandgap, and improved resistance to radiation-induced polarization [1]. We bonded 2 mm thick HF-CZT sensors with Cornell's Mixed-Mode Pixel Array ASICs, which combine analog charge integration and in-pixel digital counting to achieve single X-ray sensitivity, large full well capacity, and frame rates up to 10 kHz [2,3]. Detector characterization showed stable electron collection above 150 V bias, while hole collection remained limited by trapping even at 700 V. Temporal studies revealed non-negligible afterglow, with an unexpected increase in afterglow at higher biases, which was reduced by infrared illumination, suggesting that injected carriers reduce trapping near contact interfaces. Polarization measurements confirmed improved stability compared to conventional CZT, though polarization effects persisted, particularly with hole collection, with up to 5% signal loss and spatial distortion at high doses.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals

This paper presents design details and measurement results of LArASIC, a front-end application specific integrated circuit (ASIC) designed for low-noise readout of charge signals generated in neutrino study experiments within liquid argon time projection chambers. LArASIC comprises of 16-channels of programmable charge amplification and pulse shaping stages that provide a voltage readout proportional to the input charge and was optimized for operation at liquid argon temperature, i.e., 89 K. The chip was fabricated in a 180 nm CMOS process. Measurements at liquid nitrogen temperature, i.e., 77 K, indicate that the channel outputs have high linearity (INL < 0.1%) within the operating range, an equivalent noise charge of 534 electrons for a peaking time of 1 µs and a detector capacitance of 150 pF, and a worst-case inter-channel cross-talk of 0.35%. The paper also presents design choices made in the process of migrating LArASIC to CHARMS, an ASIC to be fabricated in a 65 nm process that includes all features provided by LArASIC, along with additional digital programmability for improved robustness and flexibility. CHARMS is intended for use in future high-energy physics experiments that require high-resolution charge or light readout with shorter pulse peaking times.

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Design of a Time-to-Digital Converter ASIC and a mini-DAQ system for the Phase-2 upgrade of the ATLAS Monitored Drift Tube detector

We present the second prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for High-Luminosity LHC operations. Compared to the first prototype, triple modular redundancy has been implemented for the configuration and flow control logic. Here, the total power consumption is increased by less than 10 mW while achieving the same time resolution and channel uniformity. A mini-DAQ system has been built to verify the front-end electronics chain with the new prototype together with other ASICs and boards in triggered mode. Cosmic ray tests with a small-diameter MDT chamber indicate that the configuration and data transmission of the readout electronics perform well. It is expected that this prototype design will be used in the final production.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specific integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifiers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verified using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond Timing

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specifc integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verifed using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2024

The CMOS Pseudo-Thyristor: a zero-static current discriminator circuit

We report a very low power discriminator circuit for pixelized detectors, called the Pseudo-Thyristor is described in this document. It is a positive feedback topology using regular PMOS and NMOS field-effect transistors (FET's) with zero static current. When a small charge is injected into the circuit, it flips rapidly due to the positive feedback and outputs a logic transition for further digitization. Simulation shows that in a 65 nm process, it is possible to achieve a detecting threshold below 5 fC while maintain the average power consumption below 10 micro-Watts when the hit occupancy is <10% for 40 MHz operation.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

Entangled Photon Pair Source Demonstrator Using the Quantum Instrumentation Control Kit System

Here, we report the first demonstration of using the Quantum Instrumentation and Control Kit (QICK) system on RFSoC-FPGA technology to drive the electro-optic intensity modulator that generate time-bin entangled photon pairs and to detect the photon signals. With the QICK system, we achieve high levels of performance metrics including coincidence-to-accidental ratio exceeding 150, and entanglement visibility exceeding 95%, consistent with performance metrics achieved using conventional waveform generators. We also demonstrate simultaneous detector readout using the digitization functional of QICK, achieving internal system synchronization time resolution of 3.2 ps. The work reported in this paper represents an explicit demonstration of the feasibility for replacing commercial waveform generators and time taggers with RFSoC-FPGA technology in the operation of a quantum network, representing a cost reduction of more than an order of magnitude.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Quality assurance test of silicon photomultipliers and electronic boards for STAR event plane detector

The event plane detector (EPD), installed in the Solenoid Tracker at the Relativistic Heavy-Ion Collider located at the Brookhaven National Laboratory is a plastic scintillator-based device that measures the reaction centrality and event plane in the forward region of the relativistic heavy-ion collisions. We used silicon photomultiplier (SiPM) arrays to detect the photons produced in the scintillator via the fiber connection. Signals from the SiPM arrays were amplified by the front-end electronic (FEE) board, and sent to the analog-to-digital converter (ADC) boards for further processing via the receiver (RX) board. The full EPD system consisted of 24 super-sectors (SSs); each SS was equipped with two SiPM boards, two FEE boards and two RX boards, and they corresponded to 744 readout channels. All these boards were mass produced at the University of Science and Technology of China, with a dedicated quality assurance (QA) procedures applied to identify any problems before deployment. This article describes the details of the QA method and the related test system. As a result, the QA test results are presented along with the discussions.

EPD↗
DOE OSTI2021

A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors

In this report a 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm 2 , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5 μV-rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

GRAPH — an readout ASIC for large MCP based detectors

We present a programmable 16 channel, mixed signal, low power readout ASIC, having the project historically named Gigasample Recorder of Analog waveforms from a PHotodetector (GRAPH). It is designed to read large aperture single photon imaging detectors using micro channel plates for charge multiplication, and measuring the detector's response on crossed strips anodes to extrapolate the incoming photon position. Each channel consists of a fast, low power and low noise charge sensitive amplifier, which provides a myriad of coarse and fine programmable options for gain and shaping settings. Further, the amplified signal is recorded using, to our knowledge novel, the Hybrid Universal sampLing Architecture (HULA) ADC. A kind of mixed signal double buffer memory, that enables concurrent waveform recording, and selected event digitized data extraction. The sampling frequency is freely adjustable between few kHz up to 125 MHz, while the chip's internal digital memory holds a history 2048 samples for each channel, with a digital headroom of 12 bits. An optimized region of interest sample-read algorithm allows to extract the information just around the event pulse peak, while selecting the next event, thus substantially reducing the operational dead time. The chip is designed in 130 nm TSMC CMOS technology, and its power consumption is around 47 mW per channel.

47 OTHER INSTRUMENTATION↗
DOE OSTI2021

Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16× 16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most probable value of around 15 fC. The discriminator generates the digital pulse, which provides the Time-Of-Arrival (TOA, leading edge) and Time-Over-Threshold (TOT, pulse width) information. The prototype of ETROC (ETROC0) that implements a single channel of analog readout circuits has been evaluated with charge injection. The jitter of the analog readout circuits, measured from the discriminator's leading edge, is better than 16 ps for a charge larger than 15 fC with the sensor capacitance. The time walk resulting from different pulse heights can be corrected using the TOT measurement. The time resolution distribution has a standard deviation of 29 ps after the time-walk correction from the charge injection. At room temperature, the preamplifier's power consumption is measured to be 0.74 mW and 1.53 mW per pixel in the low- and high-power mode, respectively. Finally, the measured power consumption of the discriminator is 0.84 mW per pixel. With the ASIC alone or the LGAD sensor, The characterization performances fulfill the ETL's challenging requirements.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade

We present the design and characterization of the first fullchain precision timing prototype ASIC, named ETL Readout Chipversion 1 (ETROC1) for the CMS MTD endcap timing layer (ETL)upgrade. The ETL utilizes Low Gain Avalanche Diode (LGAD) sensors todetect charged particles, with the goal to achieve a time resolutionof 40–50 ps per hit, and 30–40 ps per track with hits from twodetector layers. The ETROC1 is composed of a 5 × 5 pixelarray and peripheral circuits. The pixel array includes a4 × 4 active pixel array with an H-tree shaped networkdelivering clock and charge injection signals. Each active pixel iscomposed of various components, including a bump pad, a chargeinjection circuit, a pre-amplifier, a discriminator, adigital-to-analog converter, and a time-to-digital converter. Thesecomponents play essential roles as the front-end link in processingLGAD signals and measuring timing-related information. Theperipheral circuits provide clock signals and readoutfunctionalities. The size of the ETROC1 chip is7 mm× 9 mm. ETROC1 has been fabricated in a 65 nmCMOS process, and extensively tested under stimuli of chargeinjection, infrared laser, and proton beam. The time resolution ofbump-bonded ETROC1 + LGAD chipsets reaches 42–46 ps per hit in thebeam test.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

The VMM3a ASIC

The VMM3a is a custom low-noise Application Specific Integrated Circuit. It is intended to be used in the front end readout electronics of both the Micromegas and sTGC detectors of the ATLAS New Small Wheels upgrade project at CERN. It is fabricated in the 130 nm GlobalFoundries 8RF-DM process. Here, the 64 channels with highly configurable parameters, although designed for a specific project, can meet the processing needs of signals from various detector types in several other applications. In this note, the VMM3a, which is the production version of the VMM family, will be presented along with the features incorporated and its performance.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗