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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2012

Lunar Reconnaissance Orbiter (LRO) Command and Data Handling Flight Electronics Subsystem

A document describes a high-performance, modular, and state-of-the-art Command and Data Handling (C&DH) system developed for use on the Lunar Reconnaissance Orbiter (LRO) mission. This system implements a complete hardware C&DH subsystem in a single chassis enclosure that includes a processor card, 48 Gbytes of solid-state recorder memory, data buses including MIL-STD-1553B, custom RS-422, SpaceWire, analog collection, switched power services, and interfaces to the Ka-Band and S-Band RF communications systems. The C&DH team capitalized on extensive experience with hardware and software with PCI bus design, SpaceWire networking, Actel FPGA design, digital flight design techniques, and the use of VxWorks for the real-time operating system. The resulting hardware architecture was implemented to meet the LRO mission requirements. The C&DH comprises an enclosure, a backplane, a low-voltage power converter, a single-board computer, a communications interface board, four data storage boards, a housekeeping and digital input/output board, and an analog data acquisition board. The interfaces between the C&DH and the instruments and avionics are connected through a SpaceWire network, a MIL-STD-1553 bus, and a combination of synchronous and asynchronous serial data transfers over RS-422 and LVDS (low-voltage differential-signaling) electrical interfaces. The C&DH acts as the spacecraft data system with an instrument data manager providing all software and internal bus scheduling, ingestion of science data, distribution of commands, and performing science operations in real time.

Nguyen, Quang↗
NASA NTRS1994

Digital Modem Design Based on Multirate Filter Banks

A new approach for the architecture of an all digital modem design is presented. The key feature is a lower processing rate than that of the Nyquist rate (the input sampling rate) and even the symbol rate. The lower processing rate is achieved by the use of a parallel structure, based on multirate filter banks concepts. In this proposed scheme, matched filtering is implemented in the subbands of an analysis/synthesis filter bank.

digital modem design↗
NASA NTRS1981

Modular hardware synthesis using an HDL

Although hardware description languages (HDL) are becoming more and more necessary to automated design systems, their application is complicated due to the difficulty in translating the HDL description into an implementable format, nonfamiliarity of hardware designers with high-level language programming, nonuniform design methodologies and the time and costs involved in transfering HDL design software. Digital design language (DDL) suffers from all of the above problems and in addition can only by synthesized on a complete system and not on its subparts, making it unsuitable for synthesis using standard modules or prefabricated chips such as those required in LSI or VLSI circuits. The present paper presents a method by which the DDL translator can be made to generate modular equations that will allow the system to be synthesized as an interconnection of lower-level modules. The method involves the introduction of a new language construct called a Module which provides for the separate translation of all equations bounded by it.

Covington, J. A.↗
NASA NTRS1971

Arithmetic error codes - Cost and effectiveness studies for application in digital system design.

The application of error-detecting or error-correcting codes in digital computer design requires studies of cost and effectiveness tradeoffs to supplement the knowledge of their theoretical properties. General criteria for cost and effectiveness studies of error codes are developed, and results are presented for arithmetic error codes with the low-cost check modulus 2 super a - 1. Both separate (residue) and nonseparate (AN) codes are considered. The class of multiple arithmetic error codes is developed as an extension of low-cost single codes.

Avizienis, A.↗
NASA NTRS1988

Designing Estimator/Predictor Digital Phase-Locked Loops

Signal delays in equipment compensated automatically. New approach to design of digital phase-locked loop (DPLL) incorporates concepts from estimation theory and involves decomposition of closed-loop transfer function into estimator and predictor. Estimator provides recursive estimates of phase, frequency, and higher order derivatives of phase with respect to time, while predictor compensates for delay, called "transport lag," caused by PLL equipment and by DPLL computations.

Statman, J. I.↗
NASA NTRS1972

The use of linear programming techniques to design optimal digital filters for pulse shaping and channel equalization

A time domain technique is developed to design finite-duration impulse response digital filters using linear programming. Two related applications of this technique in data transmission systems are considered. The first is the design of pulse shaping digital filters to generate or detect signaling waveforms transmitted over bandlimited channels that are assumed to have ideal low pass or bandpass characteristics. The second is the design of digital filters to be used as preset equalizers in cascade with channels that have known impulse response characteristics. Example designs are presented which illustrate that excellent waveforms can be generated with frequency-sampling filters and the ease with which digital transversal filters can be designed for preset equalization.

Houts, R. C.↗
NASA NTRS1973

Computerized logic design of digital circuits

This manual presents a computer program that performs all the work required for the logic design of digital counters or sequential circuits and the simplification of Boolean logic expressions. The program provides both the experienced and inexperienced logic designer with a comprehensive logic design capability. The manual contains Boolean simplification and sequential design theory, detailed instructions for use of the program, a large number of illustrative design examples, and complete program documentation.

Sussow, S.↗
NASA NTRS1973

Apollo experience report: Guidance and control systems - Digital autopilot design development

The development of the Apollo digital autopilots (the primary attitude control systems that were used for all phases of the lunar landing mission) is summarized. This report includes design requirements, design constraints, and design philosophy. The development-process functions and the essential information flow paths are identified. Specific problem areas that existed during the development are included. A discussion is also presented on the benefits inherent in mechanizing attitude-controller logic and dynamic compensation in a digital computer.

Peters, W. H.↗
NASA NTRS1978

Digital controller design: Analysis of the annular suspension pointing system

The analog controllers of the annular suspension pointing system are designed for control of the chi, phi sub 1, and phi sub 2 bandwidth dynamics through decoupling and pole placement. Since it is virtually impossible to find an equivalent bandwidth of the overall system and establish a general eigenvalue requirement for the system, the subsystem dynamics are decoupled through state feedback and the poles are placed simultaneously to realize the desired bandwidths for the three system components. Decoupling and pole placement are also used to design the closed-loop digital system through approximation.

Kuo, B. C.↗
DOE OSTI2026

Design of digital acquisition for beam current monitor

As a part of the Proton Improvement Plan – II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, R.Turner [Fermilab]↗
DOE OSTI2025

Design of Digital Acquisition for Beam Current Monitor

As a part of the Proton Improvement Plan II (PIP-II) at Fermilab, instrumentation systems are being modernized to take advantage of the higher speeds and ease of use offered by standardized embedded systems like MicroTCA. A rear-transition module (RTM) is being designed to interface with said embedded systems. In each of the four identical channels on the RTM, the differential signal from an alternating-current current transformer (ACCT) transimpedance amplifier will again be amplified by a differential operation-amplifier, then filtered by a low-pass topology. The conditioned signal is then digitized at a maximum of 10MS/s by an analog to digital converter (ADC) integrated circuit. After digitization, the ADC passes the data to an off the shelf AdvancedMC (AMC) Xilinx FPGA module using low voltage differential signals. This paper will describe the simulation of analog circuitry for signal conditioning, simulation of digital signal integrity based on physical design as well as verification of design characteristics critical to signal integrity. This work aims to create a methodology that can be applied to future RTMs requiring application of high-speed digital design principles.

White, Turner [Fermilab] (ORCID:0009000348159256)↗
NASA NTRS2012

Analog Design for Digital Deployment of a Serious Leadership Game

This paper presents the design, development, and user testing of a leadership development simulation. The authors share lessons learned from using a design process for a board game to allow for quick and inexpensive revision cycles during the development of a serious leadership development game. The goal of this leadership simulation is to accelerate the development of leadership capacity in high-potential mid-level managers (GS-15 level) in a federal government agency. Simulation design included a mixed-method needs analysis, using both quantitative and qualitative approaches to determine organizational leadership needs. Eight design iterations were conducted, including three user testing phases. Three re-design iterations followed initial development, enabling game testing as part of comprehensive instructional events. Subsequent design, development and testing processes targeted digital application to a computer- and tablet-based environment. Recommendations include pros and cons of development and learner testing of an initial analog simulation prior to full digital simulation development.

Maxwell, Nicholas↗
NASA NTRS1981

An investigation of radiometer design using digital processing techniques

The use of digital signal processing techniques in Dicke switching radiometer design was investigated. The general approach was to develop an analytical model of the existing analog radiometer and identify factors which adversly affect its performance. A digital processor was then proposed to verify the feasibility of using digital techniques to minimize these adverse effects and improve the radiometer performance. Analysis and preliminary test results comparing the digital and analog processing approaches in radiometers design were analyzed.

Lawrence, R. W.↗
NASA NTRS1998

Characterization and Design of Digital Pointing Subsystem for Optical Communication Demonstrator

The Optical Communications Demonstrator (OCD) is a laboratory-based lasercom demonstration terminal designed to validate several key technologies, including beacon acquisition, high bandwidth tracking, precision bearn pointing, and point-ahead compensation functions. It has been under active development over the past few years. The instrument uses a CCD array detector for both spatial acquisition and high-bandwidth tracking, and a fiber coupled laser transmitter. The array detector tracking concept provides wide field-of-view acquisition and permits effective platform jitter compensation and point-ahead control using only one steering mirror. This paper describes the detailed design and characterization of the digital control loop system which includes the Fast Steering Mirror (FSM), the CCD image tracker, and the associated electronics. The objective is to improve the overall system performance using laboratory measured data. The. design of the digital control loop is based on a linear time invariant open loop model. The closed loop performance is predicted using the theoretical model. With the digital filter programmed into the OCD control software, data is collected to verify the predictions. This paper presents the results of the, system modeling and performance analysis. It has been shown that measurement data closely matches theoretical predictions. An important part of the laser communication experiment is the ability of FSM to track the laser beacon within the. required tolerances. The pointing must be maintained to an accuracy that is much smaller than the transmit signal beamwidth. For an earth orbit distance, the system must be able to track the receiving station to within a few microradians. The failure. to do so will result in a severely degraded system performance.

Racho, C.↗
NASA NTRS1971

Digital autopilots: Design considerations and simulator evaluations

The development of a digital autopilot program for a transport aircraft and the evaluation of that system's performance on a transport aircraft simulator is discussed. The digital autopilot includes three axis attitude stabilization, automatic throttle control and flight path guidance functions with emphasis on the mode progression from descent into the terminal area through automatic landing. The study effort involved a sequence of tasks starting with the definition of detailed system block diagrams of control laws followed by a flow charting and programming phase and concluding with performance verification using the transport aircraft simulation. The autopilot control laws were programmed in FORTRAN 4 in order to isolate the design process from requirements peculiar to an individual computer.

Osder, S.↗