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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Vaporization-cooled heat sink proposed for use during soldering of multiple electrical leads of packaged electronic devices to circuit boards. Heat sink includes compliant wicks held in grooves on edges of metal fixture. Wicks saturated with water. Prevents excessive increases in temperature at entrances of leads into package.
The assembly of photonics devices such as laser diodes, optical modulators, and opto-electronics multi-chip modules (OEMCM), usually requires the placement of micron size devices such as laser diodes, and sub-micron precision attachment between optical fibers and diodes or waveguide modulators (usually referred to as pigtailing). This is a very labor intensive process. Studies done by the opto-electronics (OE) industry have shown that 95 percent of the cost of a pigtailed photonic device is due to the use of manual alignment and bonding techniques, which is the current practice in industry. At Lawrence Livermore National Laboratory, we are working to reduce the cost of packaging OE devices through the use of automation. Our efforts are concentrated on several areas that are directly related to an automated process. This paper will focus on our progress in two of those areas, in particular, an automated fiber pigtailing machine and silicon micro-technology compatible with an automated process.
Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.
High humidity and temperature test (known as 85/85 tests) were performed on various III-V devices and structures to determine environmental effects in non-hermetically packaged GaAs membrane mixer diodes.
The partial discharge (PD) data presently obtained by means of a stepwise ramp technique, for the cases of high voltage (HV) components and such resin-packaged HV devices as the Space Telescope's Faint Object Camera, is acquired separately on part-way ramps to rated voltage and on the intermediate voltage plateaus. For test specimens intended for dc service, this ramp method yields more data on insulation integrity than quiescent dc measurements, especially in the case of specimens of high resistivity which causes the discharge frequency to be deceptively low at constant dc voltage. During upward ramping the voltage distribution is capacitive, and the PD behavior resembles that of an ac test. Many more pulses are obtained in the voids without the heat otherwise generated by the application of 60-Hz ac. PD histograms are presented for various materials, with and without intentional defects.
Enclosure for silicon device ensures accurate measurements of cryogenic liquids. Package holds silicon sensor in uniform compression around periphery and helps ensure accurate, stable, and repeatable pressure measurements. Mounting assembly housed in package of stainless steel. Materials selected for equality of thermal expansion and for pressure-sealing properties. Besides its high-pressure, low-temperature characteristics, package withstands vibrations as severe as 400 times standard gravitational acceleration at 0 to 2,000 Hz.
The design details and measurement results for a cooled L-band (1 to 2 GHz) balanced high electron mobility transistor (HEMT) amplifier are presented. The amplifier uses commercially available packaged HEMT devices (Fujitsu FHR02FH). At a physical temperature of 12 K, the amplifier achieves noise temperatures between 3 and 6 K over the 1 to 2 GHz band. The associated gain is approximately 20 dB.
The design details and measurement results for a cooled 1-GHz-bandwidth L-band HEMT amplifier are presented. The HEMT noise parameters were measured at a physical temperature of 12 K, and a balanced configuration was adopted. This has the advantage of providing a good input match even though the amplifiers in the two arms of the balanced circuit are poorly matched. However, there are disadvantages. The loss of the input hybrid degrades the noise temperature and coupling errors in the hybrids, and differences between the amplifiers reduce the gain and result in a noise contribution from the input load. In the amplifier described, these effects degrade the noise temperature by less than 1 K. The amplifier uses commercially available packaged HEMT devices. At a physical temperature of 12 K the amplifier achieves noise temperatures between 3 and 6 K over the 1-2-GHz band. The associated gain is about 20 dB.
Accelerated life testing techniques provide a short-cut method to investigate the reliability of electronic devices with respect to certain dominant failure mechanisms that occur under normal operating conditions. However, accelerated tests have often been conducted without knowledge of the failure mechanisms and without ensuring that the test accelerated the same mechanism as that observed under normal operating conditions. This paper summarizes common failure mechanisms in electronic devices and packages and investigates possible failure mechanism shifting during accelerated testing.
Electronic systems that are capable of operating at cryogenic temperatures will be needed for many future NASA space missions, including deep space probes and spacecraft for planetary surface exploration. In addition to being able to survive the harsh deep space environment, low-temperature electronics would help improve circuit performance, increase system efficiency, and reduce payload development and launch costs. Terrestrial applications where components and systems must operate in low-temperature environments include cryogenic instrumentation, superconducting magnetic energy storage, magnetic levitation transportation systems, and arctic exploration. An ongoing research and development project for the design, fabrication, and characterization of low-temperature electronics and supporting technologies at NASA Glenn Research Center focuses on efficient power systems capable of surviving in and exploiting the advantages of low-temperature environments. Supporting technologies include dielectric and insulating materials, semiconductor devices, passive power components, optoelectronic devices, and packaging and integration of the developed components into prototype flight hardware. An overview of the project is presented, including a description of the test facilities, a discussion of selected data from component testing, and a presentation of ongoing research activities being performed in collaboration with various organizations.
The High Frequency Instrument (HFI) on Planck will obtain all-sky images of the Cosmic Microwave Background (CMB) and other astrophysical sources of emission with resolution of 9 arcniin at 100 GHz, 7 arcmin at 143 GHz and 5 arcniin at 217, 353, 545 and 857 GHz. The HFI focal plane will contain 48 silicon nitride micromesh bolometric detectors operating from a 100 mK heat sink. Four detectors in each of the 6 bands will detect the sum of the power in both linear polarizations. An additional 4 pair of detectors will provide sensitivity to linear polarization of emission at 143, 217 and 353 GHz. We report on the development of these detectors, which are being produced at the JPL Micro Devices Laboratory, packaged at JPL Electronics Packaging, characterized at 100 mK before delivery to our HFI consortium partners at the UWCC, UK.
A light-weight, inexpensively fabricated, hermetically sealable, repairable package for small electronic or electromechanical units, having multiple connections, is described. A molded ring frame of polyamide-imide plastic (Torlon) is attached along one edge to a base plate formed of a highly heat conducting material, such as aluminum or copper. Bores are placed through a base plate within the area of the edge surface of ring frame which result in an attachment of the ring frame to the base plate during molding. Electrical leads are molded into the ring frame. The leads are L-shaped gold-plated copper wires imbedded within widened portions of the side wall of the ring frame. Within the plastic ring frame wall the leads are bent (typically, though not necessarily at 90 deg) so that they project into the interior volume of the ring frame for connection to the solid state devices.
Device, using magnetic attraction, can facilitate handling of integrated-circuit flat packages and prevent contamination and bent leads. Tool lifts packages by their cases and releases them by operation of manual plunger.
In 2007, International Rectifier (IR) introduced a new version of its DirectFET metal oxide semiconductor field effect transistor (MOSFET) packaging. The new version (referred to as 'Version 2') enhances device moisture resistance, makes surface mount (SMT) assembly of these devices to printed wiring boards (PWBs) more repeatable, and subsequent assembly inspection simpler. In the present study, the National Aeronautics Space Administration (NASA) Jet Propulsion Laboratory (JPL), in collaboration with Stellar Microelectronics (Stellar), continued an evaluation of the DirectFET that they started together in 2006. The present study focused on comparing the two versions of the DirectFET and examining the suitability of the DirectFET devices for space applications. This study evaluated both versions of two DirectFET packaged devices that had both been shown in the 2006 study to have the best electrical and thermal properties: the IRF6635 and IRF6644. The present study evaluated (1) the relative electrical and thermal performance of both versions of each device, (2) the performance through high reliability testing, and (3) the performance of these devices in combination with a range of alternate solder alloys in the extreme thermal environments of deep space....
The increasing use of power electronics, such as high-current semiconductor devices and modules, within space vehicles is driving the need to develop specialty thermal management materials in both the packaging of these discrete devices and the packaging of modules consisting of these device arrays. Developed by Applied Nanotech, Inc. (ANI), CarbAl heat transfer material is uniquely characterized by its low density, high thermal diffusivity, and high thermal conductivity. Its coefficient of thermal expansion (CTE) is similar to most power electronic materials, making it an effective base plate substrate for state-of-the-art silicon carbide (SiC) super junction transistors. The material currently is being used to optimize hybrid vehicle inverter packaging. Adapting CarbAl-based substrates to space applications was a major focus of the SBIR project work. In Phase I, ANI completed modeling and experimentation to validate its deployment in a space environment. Key parameters related to cryogenic temperature scaling of CTE, thermal conductivity, and mechanical strength. In Phase II, the company concentrated on improving heat sinks and thermally conductive circuit boards for power electronic applications.
To increase contact conductance between two mating surfaces, a conductive tape has been developed by growing dense arrays of carbon nanotubes (CNTs, graphite layers folded into cylinders) on both sides of a thermally conductive metallic foil. When the two mating surfaces are brought into contact with the conductive tape in between, the CNT arrays will adhere to the mating surface. The van der Waals force between the contacting tubes and the mating surface provides adhesion between the two mating surfaces. Even though the thermal contact conductance of a single tube-to-tube contact is small, the tremendous amount of CNTs on the surface leads to a very large overall contact conductance. Interface contact thermal resistance rises from the microroughness and the macroscopic non-planar quality of mating surfaces. When two surfaces come into contact with each other, the actual contact area may be much less than the total area of the surfaces. The real area of contact depends on the load, the surface roughness, and the elastic and inelastic properties of the surface. This issue is even more important at cryogenic temperatures, where materials become hard and brittle and vacuum is used, which prevents any gas conduction through the interstitial region. A typical approach to increase thermal contact conductance is to use thermally conducting epoxies or greases, which are not always compatible with vacuum conditions. In addition, the thermal conductivities of these compounds are often relatively low. The CNTs used in this approach can be metallic or semiconducting, depending on the folding angle and diameter. The electrical resistivity of multiwalled carbon nanotubes (MWCNTs) has been reported. MWCNTs can pass a current density and remain stable at high temperatures in air. The thermal conductivity of a MWCNT at room temperature is measured to be approximately 3,000 W/m-K, which is much larger than that of diamond. At room temperature, the thermal conductance of a 0.3 sq cm array of CNTs was measured to be as high as 10 W/K. The high thermal conductivity and the nanoscale size make CNTs ideal as thermal interface materials. The CNT-based thermal tape can be used for the thermal management of microelectronic packages and electronic systems. It also can be integrated with current device technology and packaging. The material would allow for an efficient method to manage excess heat generation without requiring any additional power. Lastly, the CNT tape can be used to enhance thermal contact conductance across two mating surfaces on some NASA missions.
The heat from high-power microdevices for space, such as Xilinx Virtex 4 and 5 (V4 and V5), has to be removed mainly through conduction in the space vacuum environment. The class-Y type packages are designed to remove the heat from the top of the package, and the most effective method to remove heat from the class-Y type packages is to attach a heat transfer device on the lid of the package and to transfer the heat to frame or chassis. When a heat transfer device is attached to the package lid, the surfaces roughness of the package lid and the heat transfer device reduces the effective contact area between the two. The reduced contact area results in increased thermal contact resistance, and a thermal interface material is required to reduce the thermal contact resistance by filling in the gap between the surfaces of the package lid and the heat transfer device. The current report describes JPL's FY14 NEPP task study on property requirements of TIM and impact of TIM properties on the packaging reliability. The current task also developed appratuses to investigate the performances of TIMs in the actual mission environment.
The history and the current status of the high temperature superconductivity space experiment (HTSSE) initiated in 1988 are briefly reviewed. The goal of the HTSSE program is to demonstrate the feasibility of incorporating high temperature superconductivity (HTS) technology into space systems. The anticipated payoffs include the development of high temperature superconductor devices for space systems; preparation and space qualification of a cryogenically cooled experimental package containing HTS devices and components; and acquisition of data for future space experiments using more complex HTS devices and subsystems. The principal HTSSE systems and devices are described.