Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “datacenter”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Security and Trust Metrics for Edge Computing

The present state of edge computing is an environment of different computing capabilities connected via a wide variety of communication paths. The energy grid is relying upon distributed energy devices connected at the edge of the internet. Consider the scenario where each edge device is customer-owned distributed energy resource (DER) that is connected via a trustworthy link to a grid service provider. Each DER keeps a local simple trust record of interactions. Information protection is provided by internet https standards, however, trust must be evaluated throughout operation. This paper presents a model for representing and evaluating trust in general and applied to the energy grid as a key example. Actors on the edge may interact with each other as well as with a central datacenter.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2023

Machine Learning Models for Network Traffic Classification in Programmable Logic

Network traffic classification via machine learning on network packet payloads has emerged as an active area of research for network security due to the high accuracy machine learning models have achieved in classifying payloads. For effective deployment as part of network security, these machine learning models must not only classify malicious packet payloads accurately, they must also identify anomalous payloads and perform inference at speeds generally faster than 10,000 packets per second to be effective. This work explores the in- ference speeds and accuracy of several neural network models implemented in programmable logic on various field programmable gate arrays (FPGA) including the Xilinx VC1902 and Xilinx Zynq Ultrascale+. This work also presents the design and performance of both an autoencoder and variational autoencoder programmed on the FPGA for identifying anomalous packet payloads. The performance benefits of the FPGA implementation for this type of packet payload inspection driven by machine learning are compared against graphics processing unit (GPU) inference implementations run on two state-of-the-art datacenter GPU devices, the NVIDIA V100 and A100. The model accuracy difference between the FPGA and GPU implementations was found to be 4% or less while the Xilinx VC1902 outperformed both the NVIDIA V100 and A100 for inference speeds on all the models explored except the variational autoencoder.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2026

A Benchmark Suite for Evaluating Scientific AI Workloads on GPUs

AI applications have been steadily increasing in the allocation portfolio among leadership computing facilities. These applications depend on deep learning frameworks with hardware acceleration and underlying software systems. With the rapid development of applications, software stacks, and hardware devices, it is essential to evaluate the performance of core operations in AI workloads for direction of optimizations and procurement of next-generation high-performance computing (HPC) infrastructures. Currently, most benchmarks lack scientific AI workloads. So, we present DeepKernelBench and the experimental results of evaluating the benchmark suite for early observations and performance comparisons on datacenter GPUs using representative workloads for scientific AI, including Attentions, General matrix multiplications, Geometrics and Fourier neural operations.

Jin, Zheming [Advanced Micro Devices (AMD)]↗
DOE OSTI2020

A Dynamically-Reconfigurable Burst-Mode Link Using a Nanosecond Photonic Switch

Fast optical circuit switching has great potential to solve scaling issues with traditional packet-switch based networks and improve bandwidth and power efficiency in datacenter and high-performance computing applications. One difficultly in utilizing a fast optical switch is that the optical signal must be rapidly reacquired after each switching event so as to not significantly impact the overall throughput of the system. In this work we present a system-level integration of a nanosecond-scale $2 \times 2$ silicon photonic switch with a 25-Gbps burst-mode receiver that can lock in 31 ns. A novel FPGA-based control plane was used to generate test data, control the silicon photonic switch and burst-mode receiver, and measure bit errors at 12.5 and 20 Gbps. Error-free links (BER $< 10^{-12}$ ) with system-level reconfiguration times below 60 ns (at 20 Gbps) and 90 ns (at 12.5 Gbps) including bit- and frame-synchronization are demonstrated.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2023

Power Conversion Systems Enabled by SiC BiDFET Device

The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. Furthermore, the matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac-ac and ac dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.

42 ENGINEERING↗
DOE OSTI2017

Large-Scale and Extreme-Scale Computing with Stranded Green Power: Opportunities and Costs

Power consumption and associated carbon emissions are increasingly critical challenges for large-scale computing. Recent research proposes exploiting stranded power-uneconomic renewable power-for green supercomputing in a system called Zero-Carbon Cloud (ZCCloud). These efforts studied production supercomputing workloads on stranded-power based computing resources, demonstrating their achievable productivity. We explore economic viability of stranded-power based supercomputing, using three datacenter total-cost-of-ownership (TOO) models to study cost-effectiveness. These studies show that ZCCloud's approach can be cost-effective in the USA today, and is even more attractive in regions with higher power prices (e.g., Japan, Germany), achieving cost advantages as large as 50 percent. Environmental and power-grid benefits are a further advantage. We also explore the sensitivity of these results to changes in hardware TOO; cheaper hardware or longer lifetimes magnify the attractiveness of stranded-power based approaches, yielding advantages as large as 91 percent. These results are robust across different TCO models. Lastly, we study extreme-scale supercomputers ( >100 MW), finding stranded-power can increase peak capability per cost by as much as 80 percent.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2022

Quantifying the Impact of Advanced Web Platforms on High Performance Computing Usage

The deployment of Science Gateways for High Performance Computing (HPC) systems can alter long-accepted usage patterns on supercomputing systems in positive ways as an ever-increasing number of users migrate their workflows to HPC systems. Idaho National Laboratory (INL) has deployed two separate advanced web platforms, Open OnDemand and NICE DCV, for integration with HPC resources to improve web accessibility for HPC users. Researchers conducted a multi-year study on how HPC usage pat- terns changed in the presence of these platforms. This work reports the results of that study and quantifies the observed impacts, including adoption by visualization and Jupyter Notebook/Lab users, decreased job submission friction, rapid uptake of HPC by Windows users, and increased overall system utilization. The most significant impacts were observed from the deployment of Open OnDemand, and this work also identifies some best practices for Open OnDemand deployment for HPC datacenters.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

A Study of Performance Portability of Low-bit Fused Matrix-Vector Multiplication Kernels in SYCL

Understanding the causes of performance gaps between a portable programming model and a vendor-specific programming model is important for improving performance portability. This paper studies performance portability of low-bit fused general matrix-vector multiplication kernels in SYCL on vendors’ graphics processing units (GPUs). This work introduces the use case, explains the kernel implementations in detail, evaluates the performance of the CUDA, HIP, and SYCL kernels on datacenter, desktop, and laptop GPUs, and investigates the causes of performance gaps. The results show that loop unrolling, kernel dispatch overhead, and sum reduction contribute to the gaps.

Jin, Zheming [ORNL] (ORCID:000000027197780X)↗
DOE OSTI2021

Optics Enabled Networks and Architectures for Data Center Cost and Power Efficiency

Bandwidth demand for datacenter networks continues as performance increases and is further fueled by the exploding demand for AI and new HPC workloads. Managing power and costs will require a range of solutions including new networking and workload specialized architectures, composable systems and optical circuit switching. In this study we focus primarily on two topics, examining the benefits of flatter networks (enabled mainly by means of co-packaged-optics-enabled switches) and the utilization improvement potential for composable (disaggregated) systems, while discussing specialized hardware and networks, and optical circuit switching more briefly.

99 GENERAL AND MISCELLANEOUS↗
DOE OSTI2024

Flexible silicon photonic architecture for accelerating distributed deep learning

The increasing size and complexity of deep learning (DL) models have led to the wide adoption of distributed training methods in datacenters (DCs) and high-performance computing (HPC) systems. However, communication among distributed computing units (CUs) has emerged as a major bottleneck in the training process. In this study, we propose Flex-SiPAC, a flexible silicon photonic accelerated compute cluster designed to accelerate multi-tenant distributed DL training workloads. Flex-SiPAC takes a co-design approach that combines a silicon photonic hardware platform with a tailored collective algorithm, optimized to leverage the unique physical properties of the architecture. The hardware platform integrates a novel wavelength-reconfigurable transceiver design and a micro-resonator-based wavelength-reconfigurable switch, enabling the system to achieve flexible bandwidth steering in the wavelength domain. The collective algorithm is designed to support reconfigurable topologies, enabling efficient all-reduce communications that are commonly used in DL training. The feasibility of the Flex-SiPAC architecture is demonstrated through two testbed experiments. First, an optical testbed experiment demonstrates the flexible routing of wavelengths by shuffling an array of input wavelengths using a custom-designed spatial-wavelength selective switch. Second, a four-GPU testbed running two DL workloads shows a 23% improvement in job completion time compared to a similarly sized leaf-spine topology. We further evaluate Flex-SiPAC using large-scale simulations, which show that Flex-SiPAC is able to reduce the communication time by 26% to 29% compared to state-of-the-art compute clusters under representative collective operations.

Wu, Zhenguo (ORCID:0000000322847985)↗
DOE OSTI2017

Electrically pumped continuous wave quantum dot lasers epitaxially grown on patterned, on-axis (001) Si

High performance III-V lasers at datacom and telecom wavelengths on on-axis (001) Si are needed for scalable datacenter interconnect technologies. We demonstrate electrically injected quantum dot lasers grown on on-axis (001) Si patterned with {111} v-grooves lying in the [110] direction. No additional Ge buffers or substrate miscut was used. The active region consists of five InAs/InGaAs dot-in-a-well layers. Here, we achieve continuous wave lasing with thresholds as low as 36 mA and operation up to 80°C.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2020

Silicon photonic chip for 16-channel wavelength division (de-)multiplexing in the O-band

We experimentally demonstrate a silicon photonic chip-scale 16-channel wavelength division multiplexer (WDM) operating in the O-band. The silicon photonic chip consists of a common-input bus waveguide integrated with a sequence of 16 spectral add-drop filters implemented by 4-port contra-directional Bragg couplers and resonant cladding modulated perturbations. The combination of these features reduces the spectral bandwidth of the filters and improves the crosstalk. An apodization of the cladding modulated perturbations between the bus and the add/drop waveguides is used to optimize the strength of the coupling coefficient in the propagation direction to reduce the intra-channel crosstalk on adjacent channels. The fabricated chip was validated experimentally with a measured intra-channel crosstalk of ∼−18.9 dB for a channel spacing of 2.6 nm. The multiplexer/demultiplexer chip was also experimentally tested with a 10 Gbps data waveform. The resulting eye-pattern indicates that this approach is suitable for datacenter WDM-based interconnects in the O-band with large aggregate bandwidths.

Davis, Jordan A. (ORCID:0000000343483295)↗
DOE OSTI2022

An Exact Algorithm for the Linear Tape Scheduling Problem

Magnetic tapes are often considered as an outdated storage technology, yet they are still used to store huge amounts of data. Their main interests are a large capacity and a low price per gigabyte, which come at the cost of a much larger file access time than on disks. With tapes, finding the right ordering of multiple file accesses is thus key to performance. Moving the reading head back and forth along a kilometer long tape has a non-negligible cost and unnecessary movements thus have to be avoided. However, the optimization of tape request ordering has rarely been studied in the scheduling literature, much less than I/O scheduling on disks. For instance, minimizing the average service time for several read requests on a linear tape remains an open question. Therefore, in this paper, we aim at improving the quality of service experienced by users of tape storage systems, and not only the peak performance of such systems. To this end, we propose a reasonable polynomial-time exact algorithm while this problem and simpler variants have been conjectured NP-hard. We also refine the proposed model by considering U-turn penalty costs accounting for inherent mechanical accelerations. Then, we propose a low-cost variant of our optimal algorithm by restricting the solution space, yet still yielding an accurate suboptimal solution. Finally, we compare our algorithms to existing solutions from the literature on logs of the mass storage management system of a major datacenter. This allows us to assess the quality of previous solutions and the improvement achieved by our low-cost algorithm. Aiming for reproducibility, we make available the complete implementation of the algorithms used in our evaluation, alongside the dataset of tape requests that is, to the best of our knowledge, the first of its kind to be publicly released.

Honoré, Valentin↗
DOE OSTI2015

Enabling Exascale Hardware and Software Design through Scalable System Virtualization (Final Report)

The purpose of this project has been to extend the state of the art of systems software for high-end computing (HEC) platforms, and to use systems software to better enable the evaluation of potential future HEC platforms, for example exascale platforms. Such platforms, and their systems software, have the goal of providing scientific computation at new scales, thus enabling new research in the physical sciences and engineering. Over time, the innovations in systems software for such platforms also become applicable to more widely used computing clusters, data centers, and clouds. This was a five-institution project, centered on the Palacios virtual machine monitor (VMM) systems software, a project begun at Northwestern, and originally developed in a previous collaboration between Northwestern University and the University of New Mexico. In this project, Northwestern (including via our subcontract to the University of Pittsburgh) contributed to the continued development of Palacios, along with other team members. We took the leadership role in (1) continued extension of support for emerging Intel and AMD hardware, (2) integration and performance enhancement of overlay networking, (3) connectivity with architectural simulation, (4) binary translation, and (5) support for modern Non-Uniform Memory Access (NUMA) hosts and guests. We also took a supporting role in support for specialized hardware for I/O virtualization, profiling, configurability, and integration with configuration tools. The efforts we led (1-5) were largely successful and executed as expected, with code and papers resulting from them. The project demonstrated the feasibility of a virtualization layer for HEC computing, similar to such layers for cloud or datacenter computing. For effort (3), although a prototype connecting Palacios with the GEM5 architectural simulator was demonstrated, our conclusion was that such a platform was less useful for design space exploration than anticipated due to inherent complexity of the connection between the instruction set architecture level and the microarchitectural level. For effort (4), we found that a code injection approach proved to be more fruitful. The results of our efforts are publicly available in the open source Palacios codebase and published papers, all of which are available from the project web site, v3vee.org. Palacios is currently one of the two codebases (the other being Sandia’s Kitten lightweight kernel) that underlies the node operating system for the DOE Hobbes Project, one of two projects tasked with building a systems software prototype for the national exascale computing effort.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

A Transformational Natural Gas Fueled Dynamic SOFC for Data Center in-Rack Power (Final Technical Report)

Data centers consume 250TWh or 1% of global electricity use in 2019. This electricity demand is expected to grow exponentially in the future. The current data center power supply relies on electric grids with diesel engines and batteries as backup; the latter is critically important because a sudden loss of power could erase crucial data, causing catastrophic economic loss. However, such a double protection architecture is costly, inefficient and polluting. In search for better in-rack power system, fuel-cell based generators have recently emerged as a promising alternative to diesel engines and batteries because of its potential to be more cost-effective, more efficient and less polluting. Among many types of fuel cells, solid oxide fuel cells stand out to be a front runner because of their ability to directly operate on natural gas that has an existing infrastructure. However, there are several critical challenges facing SOFC generators to meet the rigorous power requirements of data centers: high cost, poor reliability and more importantly, slow response to the datacenters’ dynamic load change. The unexpected overload conditions in data centers can cause fuel starvation; the latter can initiate microcracks in the anode structure, thus jeopardizing the lifetime of the SOFC generator. The current efforts to increase transient power capabilities of traditional SOFCs and therefore protect SOFC stacks from internal damage during transient loading, rely primarily upon mathematical algorithms. One of the challenges to these control methodologies is the physical limitations of the fuel delivery system such as slow response of mass flow controllers to fast power demand.

30 DIRECT ENERGY CONVERSION↗
DOE OSTI2024

Extreme Efficiency 240 Vac to Load Data Center Power Delivery Topologies and Control

The research explored innovative new circuit topologies and power converter architectures for data center power delivery, from the 240 V ac voltage at the input of a server rack, down to the less than 1 V dc power supply of the latest microprocessors. The research pursued three parallel tracks to increase the power conversion efficiency and to reduce the overall size of the servers: 1) An innovative new ac-dc power converter topology which enables improved efficiency through use of a novel direct step-down topology, well suited for the popular 48V dc power distribution. 2) A new series-stacked power delivery approach for servers comprising a large number of similar loads, such as hard drives in storage servers. The approach greatly reduces the power conversion losses, and achieves efficiency well over 99%. 3) A new family of hybrid switched-capacitor power converters that enable improved efficiency and reduced size through the use of dense ceramic capacitors and new circuit topologies that leverage GaN and low-voltage Si transistor technology. Together, the accomplished research achieved the goal of reducing the power conversion losses in datacenters, thereby reducing greenhouse gas emissions, operating costs, and overall electricity consumption.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2023

PV Inverter Systems Enabled by Monolithically Integrated SiC based Four Quadrant Power Switch (4-QPS) [BiDFET]

The purpose of this project was to develop a new breed of Power Conversion Systems (PCS) for PV integration that is enabled by the newly developed 4-Quadrant Single Die SiC Power Semiconductor Switches (4-QPS) or also referred to as “Bidirectional FET (BIDFET)”. This work includes semiconductor die development, advanced packaging, converter design, development, and testing of 4-QPS enabled hardware prototypes at 1 kW (for single phase residential application) and 10 kW (for three phase commercial application). The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four-quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs, and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. The matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac–ac and ac–dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2026

New Energy Infrastructure Outlook [Slides]

This report provides a perspective on energy infrastructure under development in the continental U.S. as of the end of 2025, focusing on those making significant progress toward achieving commercial operation. Infrastructures covered in this report include power plants, electric transmission, natural gas pipelines, liquefied natural gas terminals, and datacenters. Additionally, this report includes a section on stockpiled volumes of coal, natural gas, and petroleum.

24 POWER TRANSMISSION AND DISTRIBUTION↗