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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1981

SAR processing on the MPP

The processing of synthetic aperture radar (SAR) signals using the massively parallel processor (MPP) is discussed. The fast Fourier transform convolution procedures employed in the algorithms are described. The MPP architecture comprises an array unit (ARU) which processes arrays of data; an array control unit which controls the operation of the ARU and performs scalar arithmetic; a program and data management unit which controls the flow of data; and a unique staging memory (SM) which buffers and permutes data. The ARU contains a 128 by 128 array of bit-serial processing elements (PE). Two-by-four surarrays of PE's are packaged in a custom VLSI HCMOS chip. The staging memory is a large multidimensional-access memory which buffers and permutes data flowing with the system. Efficient SAR processing is achieved via ARU communication paths and SM data manipulation. Real time processing capability can be realized via a multiple ARU, multiple SM configuration.

Batcher, K. E.↗
NASA NTRS2003

Characterization of Pixelated Cadmium-Zinc-Telluride Detectors for Astrophysical Applications

Comparisons of charge sharing and charge loss measurements between two pixelated Cadmium-Zinc-Telluride (CdZnTe) detectors are discussed. These properties along with the detector geometry help to define the limiting energy resolution and spatial resolution of the detector in question. The first detector consists of a 1-mm-thick piece of CdZnTe sputtered with a 4x4 array of pixels with pixel pitch of 750 microns (inter-pixel gap is 100 microns). Signal readout is via discrete ultra-low-noise preamplifiers, one for each of the 16 pixels. The second detector consists of a 2-mm-thick piece of CdZnTe sputtered with a 16x16 array of pixels with a pixel pitch of 300 microns (inter-pixel gap is 50 microns). This crystal is bonded to a custom-built readout chip (ASIC) providing all front-end electronics to each of the 256 independent pixels. These detectors act as precursors to that which will be used at the focal plane of the High Energy Replicated Optics (HERO) telescope currently being developed at Marshall Space Flight Center. With a telescope focal length of 6 meters, the detector needs to have a spatial resolution of around 200 microns in order to take full advantage of the HERO angular resolution. We discuss to what degree charge sharing will degrade energy resolution but will improve our spatial resolution through position interpolation.

Gaskin, Jessica↗
NASA NTRS2012

Demonstration of the Wide-Field Imaging Interferometer Testbed Using a Calibrated Hyperspectral Image Projector

The Wide-field Imaging Interferometer testbed (WIIT) at NASA's Goddard Space Flight Center uses a dual-Michelson interferometric technique. The WIIT combines stellar interferometry with Fourier-transform interferometry to produce high-resolution spatial-spectral data over a large field-of-view. This combined technique could be employed on future NASA missions such as the Space Infrared Interferometric Telescope (SPIRIT) and the Sub-millimeter Probe of the Evolution of Cosmic Structure (SPECS). While both SPIRIT and SPECS would operate at far-infrared wavelengths, the WIIT demonstrates the dual-interferometry technique at visible wavelengths. The WIIT will produce hyperspectral image data, so a true hyperspectral object is necessary. A calibrated hyperspectral image projector (CHIP) has been constructed to provide such an object. The CHIP uses Digital Light Processing (DLP) technology to produce customized, spectrally-diverse scenes. CHIP scenes will have approximately 1.6-micron spatial resolution and the capability of . producing arbitrary spectra in the band between 380 nm and 1.6 microns, with approximately 5-nm spectral resolution. Each pixel in the scene can take on a unique spectrum. Spectral calibration is achieved with an onboard fiber-coupled spectrometer. In this paper we describe the operation of the CHIP. Results from the WIIT observations of CHIP scenes will also be presented.

Bolcar, Matthew R.↗
DOE OSTI2021

System-on-Chip approach microwave diagnostics development for burning plasma

System-on-chip (SoC) millimeter wave integrated circuit technology has been developed and employed in chip heterodyne radiometers in Electron Cyclotron Emission Imaging (ECEI) and Microwave Imaging Reflectometer (MIR) on the DIII-D tokamak for 2D electron temperature and density fluctuation diagnostics. The W-band (75-110 GHz) ECEI system has been employed with 20 poloidal horn receiver modules with customized monolithic integrated circuit chips and internal local oscillator coupling path. The new SoC approach demonstrates > 30 dB additional gain on the receiver and 95% electronics noise suppression compared to the previous Schottky diode mixer array . An F-band (110-140 GHz) receiver chip has been developed to measure MHD and turbulence behavior on the DIII-D high-field side, such as Alfven eigenmodes. Furthermore, it can image pedestal structure evolution on fusion facilities with stronger magnetic fields, such as ASDEX-U, EAST, HL-2M, and LHD. The F-band chip performance has been tested in the laboratory. Also, V-band (55-75 GHz) transmitter and receiver modules (55-75 GHz) have been developed for DIII-D and NSTX-U Furthermore, microwave Imaging Reflectometer (MIR) application suitability for 2D density fluctuation imaging on the pedestal region.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
NASA NTRS1991

Single board system for fuzzy inference

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

Symon, James R.↗
NASA NTRS1979

Future trends in image processing software and hardware

JPL image processing applications are examined, considering future trends in fields such as planetary exploration, electronics, astronomy, computers, and Landsat. Attention is given to adaptive search and interrogation of large image data bases, the display of multispectral imagery recorded in many spectral channels, merging data acquired by a variety of sensors, and developing custom large scale integrated chips for high speed intelligent image processing user stations and future pipeline production processors.

Green, W. B.↗
NASA NTRS1994

SRAM Detector Calibration

Custom proton sensitive SRAM chips are being flown on the BMDO Clementine missions and Space Technology Research Vehicle experiments. This paper describes the calibration procedure for the SRAM proton detectors and their response to the space environment.

SRAM BMDO Clementine↗
NASA NTRS1992

Design and qualification of the SEU/TD Radiation Monitor chip

This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX). The Radiation Monitor chip consists of a custom-designed 4-bit SRAM for heavy ion detection and three MOSFET's for monitoring total dose. In addition the Radiation Monitor chip was tested along with three diagnostic chips: the processor monitor and the reliability and fault chips. These chips revealed the quality of the CMOS fabrication process. The SEU/TD Radiation Monitor chip had an initial functional yield of 94.6 percent. Forty-three (43) SEU SRAM's and 14 Total Dose MOSFET's passed the hermeticity and final electrical tests and were delivered to LL.

Buehler, Martin G.↗
DOE OSTI2023

A user-friendly plug-and-play cyclic olefin copolymer-based microfluidic chip for room-temperature, fixed-target serial crystallography

Over the past two decades, serial X-ray crystallography has enabled the structure determination of a wide range of proteins. With the advent of X-ray free-electron lasers (XFELs), ever-smaller crystals have yielded high-resolution diffraction and structure determination. A crucial need to continue advancement is the efficient delivery of fragile and micrometre-sized crystals to the X-ray beam intersection. This paper presents an improved design of an all-polymer microfluidic `chip' for room-temperature fixed-target serial crystallography that can be tailored to broadly meet the needs of users at either synchrotron or XFEL light sources. The chips are designed to be customized around different types of crystals and offer users a friendly, quick, convenient, ultra-low-cost and robust sample-delivery platform. Compared with the previous iteration of the chip [Gilbile et al. (2021), Lab Chip , 21 , 4831–4845], the new design eliminates cleanroom fabrication. It has a larger imaging area to volume, while maintaining crystal hydration stability for both in situ crystallization or direct crystal slurry loading. Crystals of two model proteins, lysozyme and thaumatin, were used to validate the effectiveness of the design at both synchrotron (lysozyme and thaumatin) and XFEL (lysozyme only) facilities, yielding complete data sets with resolutions of 1.42, 1.48 and 1.70 Å, respectively. Overall, the improved chip design, ease of fabrication and high modifiability create a powerful, all-around sample-delivery tool that structural biologists can quickly adopt, especially in cases of limited sample volume and small, fragile crystals.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS1989

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.↗
DOE OSTI2024

Investigating resource-efficient neutron/gamma classification ML models targeting eFPGAs

There has been considerable interest and resulting progress in implementing machine learning (ML) models in hardware over the last several years from the particle and nuclear physics communities. A big driver has been the release of the Python package, hls4ml, which has enabled porting models specified and trained using Python ML libraries to register transfer level (RTL) code. So far, the primary end targets have been commercial field-programmable gate arrays (FPGAs) or synthesized custom blocks on application specific integrated circuits (ASICs). However, recent developments in open-source embedded FPGA (eFPGA) frameworks now provide an alternate, more flexible pathway for implementing ML models in hardware. These customized eFPGA fabrics can be integrated as part of an overall chip design. In general, the decision between a fully custom, eFPGA, or commercial FPGA ML implementation will depend on the details of the end-use application. In this work, we explored the parameter space for eFPGA implementations of fully-connected neural network (fcNN) and boosted decision tree (BDT) models using the task of neutron/gamma classification with a specific focus on resource efficiency. We used data collected using an AmBe sealed source incident on Stilbene, which was optically coupled to an OnSemi J-series silicon photomultiplier (SiPM) to generate training and test data for this study. We investigated relevant input features and the effects of bit-resolution and sampling rate as well as trade-offs in hyperparameters for both ML architectures while tracking total resource usage. The performance metric used to track model performance was the calculated neutron efficiency at a gamma leakage of 10 -3 . The results of the study will be used to aid the specification of an eFPGA fabric, which will be integrated as part of a test chip.

47 OTHER INSTRUMENTATION↗
DOE OSTI2018

Test beam demonstration of silicon microstrip modules with transverse momentum discrimination for the future CMS tracking detector

A new CMS Tracker is under development for operation at the High Luminosity LHC from 2026 onwards. It includes an outer tracker based on dedicated modules that will reconstruct short track segments, called stubs, using spatially coincident clusters in two closely spaced silicon sensor layers. These modules allow the rejection of low transverse momentum track hits and reduce the data volume before transmission to the first level trigger. The inclusion of tracking information in the trigger decision is essential to limit the first level trigger accept rate. A customized front-end readout chip, the CMS Binary Chip (CBC), containing stub finding logic has been designed for this purpose. A prototype module, equipped with the CBC chip, has been constructed and operated for the first time in a 4 GeemVem/emc positron beam at DESY. The behaviour of the stub finding was studied for different angles of beam incidence on a module, which allows an estimate of the sensitivity to transverse momentum within the future CMS detector. A sharp transverse momentum threshold around 2 emVem/emc was demonstrated, which meets the requirement to reject a large fraction of low momentum tracks present in the LHC environment on-detector. This is the first realistic demonstration of a silicon tracking module that is able to select data, based on the particle's transverse momentum, for use in a first level trigger at the LHC . The results from this test are described here.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2003

Experiences with Lab-on-a-chip Technology in Support of NASA Supported Research

Under the auspices of the Microgravity Sciences and Application Department at Marshall Space Flight Center, we have custom designed and fabricated a lab-on-a-chip (LOC) device, along with Caliper Technologies, for macromolecular crystal growth. The chip has been designed to deliver specified proportions of up-to five various constituents to one of two growth wells (on-chip) for crystal growth. To date, we have grown crystals of thaumatin, glucose isomerase and appoferitin on the chip. The LOC approach offered many advantages that rendered it highly suitable for space based hardware to perform crystal growth on the International Space Station. The same hardware that was utilized for the crystal growth investigations, has also been used by researchers at Glenn Research Center to investigate aspects of microfluidic phenomenon associated with two-phase flow. Additionally, our LOCAD (Lab-on-a-chip Application Development) team has lent its support to Johnson Space Center s Modular Assay for Solar System Exploration project. At present, the LOCAD team is working on the design and build of a unique lab-on-a-chip breadboard control unit whose function is not commercially available. The breadboard can be used as a test bed for the development of chip size labs for environmental monitoring, crew health monitoring assays, extended flight pharmacological preparations, and many more areas. This unique control unit will be configured for local use and/or remote operation, via the Internet, by other NASA centers. The lab-on-a-chip control unit is being developed with the primary goal of meeting Agency level strategic goals.

Monaco, Lisa↗
DOE OSTI2018

LArPix: demonstration of low-power 3D pixelated charge readout for liquid argon time projection chambers

In this work, we report the demonstration of a low-power pixelated readout system designed for three-dimensional ionization charge detection and digital readout of liquid argon time projection chambers (LArTPCs) . Unambiguous 3D charge readout was achieved using a custom-designed system-on-a-chip ASIC (LArPix) to uniquely instrument each pad in a pixelated array of charge-collection pads. The LArPix ASIC, manufactured in 180 nm bulk CMOS, provides 32 channels of charge-sensitive amplification with self-triggered digitization and multiplexed readout at temperatures from 80 K to 300 K . Using an 832-channel LArPix-based readout system with 3 mm spacing between pads, we demonstrated low-noise (0<50 e - RMS equivalent noise charge) and very low-power (<100 μW/channel) ionization signal detection and readout . The readout was used to successfully measure the three-dimensional ionization distributions of cosmic rays passing through a LArTPC, free from the ambiguities of existing projective techniques. The system design relies on standard printed circuit board manufacturing techniques, enabling scalable and low-cost production of large-area readout systems using common commercial facilities. This demonstration overcomes a critical technical obstacle for operation of LArTPCs in high-occupancy environments, such as the near detector site of the Deep Underground Neutrino Experiment (DUNE) .

47 OTHER INSTRUMENTATION↗
DOE OSTI2015

Stress and Strain Modeling of Low Temperature Cofired Ceramic (LTCC) Seal Frame and Lid

Low temperature cofired ceramic (LTCC) is established as an excellent packaging technology for high reliability, high density microelectronics. LTCC multichip modules (MCMs) comprising both ‘surface mount’ and ‘chip and wire’ technologies provide additional customization for performance. Long term robustness of the packages is impacted by the selection of seal frame and lid materials used to enclose the components inside distinct rooms in LTCC MCMs. An LTCC seal frame and lid combination has been developed that is capable of meeting the sealing and electromagnetic shielding requirements of MCMs. Here, we analyze the stress and strain performance of various seal frame and lid materials, sealing materials, and configurations. The application for the MCM will affect selection of the seal frame, lid, and sealing materials based on this analysis.

36 MATERIALS SCIENCE↗
NASA NTRS1986

Prototyping and implementing flight qualifiable semicustom CMOS P-well bulk integrated circuits in the JPL environment

Presently, there are many difficulties associated with implementing application specific custom or semi-custom (standard cell based) integrated circuits (ICs) into JPL flight projects. One of the primary difficulties is developing prototype semi-custom integrated circuits for use and evaluation in engineering prototype flight hardware. The prototype semi-custom ICs must be extremely cost-effective and yet still representative of flight qualifiable versions of the design. A second difficulty is encountered in the transport of the design from engineering prototype quality to flight quality. Normally, flight quality integrated circuits have stringent quality standards, must be radiation resistant and should consume minimal power. It is often not necessary or cost effective, however, to impose such stringent quality standards on engineering models developed for systems analysis in controlled lab environments. This article presents work originally initiated for ground based applications that also addresses these two problems. Furthermore, this article suggests a method that has been shown successful in prototyping flight quality semi-custom ICs through the Metal Oxide Semiconductor Implementation Service (MOSIS) program run by the University of Southern California's Information Sciences Institute. The method has been used successfully to design and fabricate through the MOSIS three different semi-custom prototype CMOS p-well chips. The three designs make use of the work presented and were designed consistent with design techniques and structures that are flight qualifiable, allowing one hour transfer of the design from engineering model status to flight qualifiable foundry-ready status through methods outlined in this article.

Olson, E. M.↗
NASA NTRS1995

A CCD offset guider for the KAO

We describe a focal plane guider for the Kuiper Airborne Observatory which consists of a CCD camera interfaced to an AMIGA personal computer. The camera is made by Photometrics Ltd. and utilizes a Thomson 576 x 384 pixel CCD chip operated in Frame Transfer mode. Custom optics produce a scale of 2.4 arc-sec/pixel, yielding an approx. 12 ft. diameter field of view. Chopped images of stars with HST Guide Star Catalog magnitudes fainter than 14 have been used for guiding at readout rates greater than or equal to 0.5 Hz. The software includes automatic map generation, subframing and zooming, and correction for field rotation when two stars are in the field of view.

Colgan, Sean W. J.↗
NASA NTRS1990

VLSI chip-set for data compression using the Rice algorithm

A full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.

Venbrux, J.↗