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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1978

Apparatus including a plurality of spaced transformers for locating short circuits in cables

A cable fault locator is described for sensing faults such as short circuits in power cables. The apparatus includes a plurality of current transformers strategically located along a cable. Trigger circuits are connected to each of the current transformers for placing a resistor in series with a resistive element responsive to an abnormally high current flowing through that portion of the cable. By measuring the voltage drop across the resistive element, the location of the fault can be determined.

Cason, R. L.↗
NASA NTRS1975

The probability of a correct output from a combinational circuit

The paper discusses two methods to evaluate the signal reliability of the output of logical circuits. It is known that faults present in a circuit will not always cause the output of the circuit to be incorrect. The first method evaluates the contribution of each fault to the reliability of the circuit and requires the enumeration of the behavior of each fault in the entire fault set. The use of McCluskey and Clegg's characterization of faulty networks by evaluating the functional equivalence classes of the network is a way to reduce the amount of computation involved. The second method uses a probabilistic model of logical circuits and consists of straightforward operations which can easily be automated. The method also yields the signal reliability and has the capability of very easily specifying the individual fault probabilities of all the circuit lines independently.

Ogus, R. C.↗
NASA NTRS1980

Detector verifier for circuit analyzers

Economical tool checks operation of automatic circuit analyzer. Each loop is addressed directly from analyzer console by switching internal analyzer bridge to resistance equal that of connecting cable plus specified limiting test value. Procedure verifies whether detected faults in circuit under test are actually due to analyzer malfunction. Standard-length universal test cables make it possible to shift detector tool from cable to cable without resistance compensation.

Pope, D. L.↗
NASA NTRS1991

High reliability megawatt transformer/rectifier

The goal of the two phase program is to develop the technology and design and fabricate ultralightweight high reliability DC to DC converters for space power applications. The converters will operate from a 5000 V dc source and deliver 1 MW of power at 100 kV dc. The power weight density goal is 0.1 kg/kW. The cycle to cycle voltage stability goals was + or - 1 percent RMS. The converter is to operate at an ambient temperature of -40 C with 16 minute power pulses and one hour off time. The uniqueness of the design in Phase 1 resided in the dc switching array which operates the converter at 20 kHz using Hollotron plasma switches along with a specially designed low loss, low leakage inductance and a light weight high voltage transformer. This approach reduced considerably the number of components in the converter thereby increasing the system reliability. To achieve an optimum transformer for this application, the design uses four 25 kV secondary windings to produce the 100 kV dc output, thus reducing the transformer leakage inductance, and the ac voltage stresses. A specially designed insulation system improves the high voltage dielectric withstanding ability and reduces the insulation path thickness thereby reducing the component weight. Tradeoff studies and tests conducted on scaled-down model circuits and using representative coil insulation paths have verified the calculated transformer wave shape parameters and the insulation system safety. In Phase 1 of the program a converter design approach was developed and a preliminary transformer design was completed. A fault control circuit was designed and a thermal profile of the converter was also developed.

Zwass, Samuel↗
NASA NTRS1982

Photovoltaic array reliability optimization

An overview of the photovoltaic array reliability problem is presented, and a high reliability/minimum cost approach to this problem is presented. Design areas covered are cell failure, interconnect fatigue, and electrical insulation breakdown, and three solution strategies are discussed. The first involves controlling component failures in the solar cell (cell cracking, cell interconnects) and at the module level (must be statistically treated). Second, a fault tolerant circuit is designed which reduces array degradation, improves module yield losses, and controls hot-spot heating. Third, cost optimum module replacement strategies are also effective in reducing array degradation. This can be achieved by minimizing the life-cycle energy cost of the photovoltaic system. The integration of these solutions is aimed at reducing the 0.01% failure rate.

Ross, R. G., Jr.↗
NASA NTRS1982

Development of photovoltaic array and module safety requirements

Safety requirements for photovoltaic module and panel designs and configurations likely to be used in residential, intermediate, and large-scale applications were identified and developed. The National Electrical Code and Building Codes were reviewed with respect to present provisions which may be considered to affect the design of photovoltaic modules. Limited testing, primarily in the roof fire resistance field was conducted. Additional studies and further investigations led to the development of a proposed standard for safety for flat-plate photovoltaic modules and panels. Additional work covered the initial investigation of conceptual approaches and temporary deployment, for concept verification purposes, of a differential dc ground-fault detection circuit suitable as a part of a photovoltaic array safety system.

Source record↗
NASA NTRS1985

Hall-Effect Ground-Fault Interruptor

Tested ground-fault interruption circuit utilizing Hall-effect device to sense differential current in magnetic core tips and opens circuit.

Okin, L.↗
NASA NTRS1985

Electrical safety requirements: Implications for the module designer

Commercial photovoltaic array installations, which include residential and intermediate applications, are subject to building and electrical codes and to product safety standards. The National Electrical Code (NEC) Article 690, titled Solar Photovoltaic Systems, contains provisions defining acceptable levels of system safety and emphasizes the system design and its installation. The Underwriters Laboratories, Inc. (UL), document titled: Proposed First Edition of the Standard for Flat Plate Photovoltaic Modules and Panels, UL-1703, identifies module and panel construction requirements that ensure product safety. Together these documents describe requirements intended to minimize hazards such as shock and fire. Although initial focus of these requirements is on single crystal silicon modules, they are generic in nature, and are equally applicable to high voltage ( 30 Vdc), multikilowatt, thin film systems. A major safety concern is insulation breakdown within the module or array wiring system, or discontinuities within the electrical conductors. These failures can result in ground faults, in circuit arcs, or exposure to hazardous electrical parts. Safeguards are discussed.

Sugimura, R. S.↗
NASA NTRS1993

Fault detection in digital and analog circuits using an i(DD) temporal analysis technique

An i(sub DD) temporal analysis technique which is used to detect defects (faults) and fabrication variations in both digital and analog IC's by pulsing the power supply rails and analyzing the temporal data obtained from the resulting transient rail currents is presented. A simple bias voltage is required for all the inputs, to excite the defects. Data from hardware tests supporting this technique are presented.

Beasley, J.↗
NASA NTRS2009

Estimation of Faults in DC Electrical Power System

This paper demonstrates a novel optimization-based approach to estimating fault states in a DC power system. Potential faults changing the circuit topology are included along with faulty measurements. Our approach can be considered as a relaxation of the mixed estimation problem. We develop a linear model of the circuit and pose a convex problem for estimating the faults and other hidden states. A sparse fault vector solution is computed by using 11 regularization. The solution is computed reliably and efficiently, and gives accurate diagnostics on the faults. We demonstrate a real-time implementation of the approach for an instrumented electrical power system testbed, the ADAPT testbed at NASA ARC. The estimates are computed in milliseconds on a PC. The approach performs well despite unmodeled transients and other modeling uncertainties present in the system.

Gorinevsky, Dimitry↗
NASA NTRS1971

DALG: A program for test pattern generation in combinational logical circuits

A user's manual for a computer program DALG which generates test patterns for detecting faults in combinational logic circuits containing up to 200 logical gates is presented. The gates may be of logical types AND, OR, NAND, NOR, NOT, or Exclusive OR is presented. The faults may be any one gate or input struck at a fixed value (0 or 1). In addition to test pattern generation DALG will also determine whether or not the given test pattern will detect given faults in a circuit. Sample problems are given along with input data sheets and printed output to illustrate the capabilities of the program.

Source record↗
NASA NTRS2012

Dust-Tolerant Intelligent Electrical Connection System

Faults in wiring systems are a serious concern for the aerospace and aeronautic (commercial, military, and civilian) industries. Circuit failures and vehicle accidents have occurred and have been attributed to faulty wiring created by open and/or short circuits. Often, such circuit failures occur due to vibration during vehicle launch or operation. Therefore, developing non-intrusive fault-tolerant techniques is necessary to detect circuit faults and automatically route signals through alternate recovery paths while the vehicle or lunar surface systems equipment is in operation. Electrical connector concepts combining dust mitigation strategies and cable diagnostic technologies have significant application for lunar and Martian surface systems, as well as for dusty terrestrial applications. The dust-tolerant intelligent electrical connection system has several novel concepts and unique features. It combines intelligent cable diagnostics (health monitoring) and automatic circuit routing capabilities into a dust-tolerant electrical umbilical. It retrofits a clamshell protective dust cover to an existing connector for reduced gravity operation, and features a universal connector housing with three styles of dust protection: inverted cap, rotating cap, and clamshell. It uses a self-healing membrane as a dust barrier for electrical connectors where required, while also combining lotus leaf technology for applications where a dust-resistant coating providing low surface tension is needed to mitigate Van der Waals forces, thereby disallowing dust particle adhesion to connector surfaces. It also permits using a ruggedized iris mechanism with an embedded electrodynamic dust shield as a dust barrier for electrical connectors where required.

Lewis, Mark↗
NASA NTRS1990

Functional requirements for an intelligent RPC

An intelligent remote power controller (RPC) based on microcomputer technology can implement advanced functions for the accurate and secure detection of all types of faults on a spaceborne electrical distribution system. The intelligent RPC will implement conventional protection functions such as overcurrent, under-voltage, and ground fault protection. Advanced functions for the detection of soft faults, which cannot presently be detected, can also be implemented. Adaptive overcurrent protection changes overcurrent settings based on connected load. Incipient and high-impedance fault detection provides early detection of arcing conditions to prevent fires, and to clear and reconfigure circuits before soft faults progress to a hard-fault condition. Power electronics techniques can be used to implement fault current limiting to prevent voltage dips during hard faults. It is concluded that these techniques will enhance the overall safety and reliability of the distribution system.

Aucoin, B. M.↗
NASA NTRS1983

Hardware Fault Simulator for Microprocessors

Breadboarded circuit is faster and more thorough than software simulator. Elementary fault simulator for AND gate uses three gates and shaft register to simulate stuck-at-one or stuck-at-zero conditions at inputs and output. Experimental results showed hardware fault simulator for microprocessor gave faster results than software simulator, by two orders of magnitude, with one test being applied every 4 microseconds.

Hess, L. M.↗
NASA NTRS1985

The development of an interim generalized gate logic software simulator

A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.

Mcgough, J. G.↗