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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Random Circuits in the Black Hole Interior

In this paper, we present a quantitative holographic relation between a microscopic measure of randomness and the geometric length of the wormhole in the black hole interior. To this end, we perturb an AdS black hole with Brownian semiclassical sources, implementing the continuous version of a random quantum circuit for the black hole. We use the random circuit to prepare ensembles of states of the black hole whose semiclassical duals contain Einstein-Rosen (ER) caterpillars: long cylindrical wormholes with large numbers of matter inhomogeneities, of linearly growing length with the circuit time. In this setup, we show semiclassically that the ensemble of ER caterpillars of average length $k\ell_Δ$ and matter correlation scale $\ell_Δ$ forms an approximate quantum state $k$-design of the black hole. At exponentially long circuit times, the ensemble of ER caterpillars becomes polynomial-copy indistinguishable from a collection of random states of the black hole. We comment on the implications of these results for holographic circuit complexity and for the holographic description of the black hole interior.

FOS: Physical sciences↗
NASA NTRS1972

An ingestible temperature-transmitter

Pill-sized transmitter measures deep body temperature in studies of circadian rhythm and indicates general health. Ingestible device is a compromise between accuracy, circuit complexity, size and transmission range.

Pope, J. M.↗
NASA NTRS1972

A high speed sequential decoder

The performance and theory of operation for the High Speed Hard Decision Sequential Decoder are delineated. The decoder is a forward error correction system which is capable of accepting data from binary-phase-shift-keyed and quadriphase-shift-keyed modems at input data rates up to 30 megabits per second. Test results show that the decoder is capable of maintaining a composite error rate of 0.00001 at an input E sub b/N sub o of 5.6 db. This performance has been obtained with minimum circuit complexity.

Lum, H., Jr.↗
NASA NTRS1974

Converter design techniques and applications

The design of transistorized voltage converters of the series, shunt, and switching types is developed and explained. The shunt converter has the smallest size, lowest weight, and lowest parts count. Regulation and stability are very good but efficiency is poor. The series converter is somewhat larger in size, heavier, uses more parts, and has an order of magnitude (10 to 1) decrease in regulation performance in comparison with the shunt converter. The switching converter tends to be a compromise with increased size, weight, and circuit complexity to gain in efficiency and regulation over a series converter. A switching converter will usually exhibit ringing in the output filter for some types of loads so it has only fair stability performance.-

Lalli, V. R.↗
NASA NTRS1976

Advanced space system concepts and their orbital support needs (1980 - 2000). Volume 2: Final report

The results are presented of a study which identifies over 100 new and highly capable space systems for the 1980-2000 time period: civilian systems which could bring benefits to large numbers of average citizens in everyday life, much enhance the kinds and levels of public services, increase the economic motivation for industrial investment in space, expand scientific horizons; and, in the military area, systems which could materially alter current concepts of tactical and strategic engagements. The requirements for space transportation, orbital support, and technology for these systems are derived, and those requirements likely to be shared between NASA and the DoD in the time period identified. The high leverage technologies for the time period are identified as very large microwave antennas and optics, high energy power subsystems, high precision and high power lasers, microelectronic circuit complexes and data processors, mosaic solid state sensing devices, and long-life cryogenic refrigerators.

Bekey, I.↗
NASA NTRS1976

A bandwidth-compressive modulation system

The phrase 'bandwidth-compressive modulation' means that the compression is achieved not by removing redundancy from the data (data compression), but rather by modulating the carrier phase and amplitude with blocks of data bits. The modulation described here is quadrature amplitude shift keying (QASK), a logical extension of quadrature phase shift keying, (QPSK, or quadriphase). QASK is a cost-effective form of combined phase-and-amplitude modulation. That is, n-bit QASK, like most phase-amplitude forms of modulation, requires considerably less transmitter power than comparably performing n-PSK, while among the class of all n-bit phase-modulation types, n-bit QASK performs nearly optimally but requires the least circuit complexity. A simple, unique microwave transmitter is described which provides high-rate QASK modulation with 4:1 bandwidth compression. A suppressed carrier multiple-loop QASK receiver provides the necessary phase tracking, automatic gain control (AGC), and symbol timing.

Smith, J. G.↗
NASA NTRS1976

Static inverter with synchronous output waveform synthesized by time-optimal-response feedback

Time-optimal-response 'bang-bang' or 'bang-hang' technique, using four feedback control loops, synthesizes static-inverter sinusoidal output waveform by self-oscillatory but yet synchronous pulse-frequency-modulation (SPFM). A single modular power stage per phase of ac output entails the minimum of circuit complexity while providing by feedback synthesis individual phase voltage regulation, phase position control and inherent compensation simultaneously for line and load disturbances. Clipped sinewave performance is described under off-limit load or input voltage conditions. Also, approaches to high power levels, 3-phase arraying and parallel modular connection are given.

Kernick, A.↗
NASA NTRS1978

Designing low cost receivers for general aviation users

Approaches to the design of a low cost receiver which meets all IFR requirements for 2D area navigation are discussed. These include: (1) using current technology with a minimum of specialized LSI, a minimum of circuit complexity, and minimal use of critical components; (2) emphasized microprocessor technology; and (3) a special analog/digital chip fabrication. A low cost GPS receiver configuration with a single sequencing tracking channel is examined. Problem areas are indicated.

Natali, F. D.↗
NASA NTRS1980

GPS/REFSAT definition study report for low-cost terminals

A relay transponder, located either on a satellite in geostationary orbit or on a local tower to relay acquisition-aiding data, ephemerides, etc, from a ground-based remote control station to a GPS civil user terminal located on a ship or land-transportation vehicle is described. Termed REFSAT (Reference Satellite), this concept reduces the circuit complexity and cost of user terminals. The various systems needed to implement the REFSAT concept for low-cost, GPS civil terminals are defined. The GPS/REFSAT system compatible with the NAVSTAR GPS system consists of a geostationary relay satellite, civil user terminals, and the central facility which performs operations common to all users for relay via the space segment. A GPS/REFSAT system utilizing a local tower for the relay transponder is described, results of a study of civil user requirements are presented, and specifications for the GPS/REFSAT system and its individual segments are included.

Source record↗
NASA NTRS1991

Application of convolve-multiply-convolve SAW processor for satellite communications

There is a need for a satellite communications receiver than can perform simultaneous multi-channel processing of single channel per carrier (SCPC) signals originating from various small (mobile or fixed) earth stations. The number of ground users can be as many as 1000. Conventional techniques of simultaneously processing these signals is by employing as many RF-bandpass filters as the number of channels. Consequently, such an approach would result in a bulky receiver, which becomes impractical for satellite applications. A unique approach utilizing a realtime surface acoustic wave (SAW) chirp transform processor is presented. The application of a Convolve-Multiply-Convolve (CMC) chirp transform processor is described. The CMC processor transforms each input channel into a unique timeslot, while preserving its modulation content (in this case QPSK). Subsequently, each channel is individually demodulated without the need of input channel filters. Circuit complexity is significantly reduced, because the output frequency of the CMC processor is common for all input channel frequencies. The results of theoretical analysis and experimental results are in good agreement.

Lie, Y. S.↗
NASA NTRS1986

Practical design of magnetic heading sensors

Although fluxgate magnetometers have been in use for many years, and a number of theoretical studies of these sensors are available, very little information has been published on the engineering choices relating to the detailed design of magnetometers intended for navigational applications in aircraft and other vehicles. This paper addresses some of the problems encountered in the design of the sensing head, the choice of operating mode, and the design of the supporting electronics for a simple low-cost magnetometer system which will produce a digital readout of the magnetic heading of the vehicle in which it is mounted. A major goal of this study has been to develop a design which minimizes circuit complexity, is easy to fabricate and calibrate, and utilizes a minimum of specialized components. Such a magnetometer system is intended either as a stand-alone indicating instrument or as a source of magnetic heading information for a more sophisticated navigational system.

Garner, H. D.↗
NASA NTRS2018

Yearlong 500 °C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, upscaling, and testing of 500°C durable two-level interconnect 4H-SiC JFET IC technology undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500°C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016.

Neudeck, Philip G.↗
DOE OSTI2021

Majorana pair based qubits for fault tolerant quantum computing architecture using superconducting gold surface states

Under certain conditions, a fermion in a superconductor can separate in space into two parts known as Majorana zero modes, which are immune to decoherence from local noise sources and are attractive building blocks for quantum computers. Here we disclose a metal-based heterostructure platform to produce these Majorana zero modes which utilizes the surface states of certain metals in combination with a ferromagnetic insulator and a superconductor. This platform has the advantage of having a robust energy scale and the possibility of realizing complex circuit designs using lithographic methods. The Majorana zero modes are interrogated using planar tunnel junctions and electrostatic gates to selectively tunnel into designated pairs of Majorana zero modes. We give example of qubit designs and circuits that are particularly suitable for the metal-based heterostructures.

Moodera, Jagadeesh S.↗
DOE OSTI2026

Exact chiral symmetry with quantum signal processing

We give a quantum signal processing (QSP) algorithm for the overlap fermion Hamiltonian which preserves the Ginsparg-Wilson relation up to a controllable error $ε_e$. Quantum simulations of Dirac fermions with exact chiral symmetry are thus nearly free: applying the overlap Hamiltonian costs only a factor logarithmic in $ε_e$ more than the Wilson-Dirac Hamiltonian. Comparing to domain-wall fermions, a mild overhead is found in circuit complexity while reducing qubit costs. We show how QSP effectively constructs an extra dimension when simulating the overlap operator, illustrating that the scaling of quantum algorithms reflects the deeper physics of overlap fermions arising at the boundary of domain-wall fermions.

Lamm, Henry [Fermilab] (ORCID:0000000330330791)↗
NASA NTRS2004

Design Space Issues for Intrinsic Evolvable Hardware

This paper discusses the problem of increased programming time for intrinsic evolvable hardware (EM) as the complexity of the circuit grows. As the circuit becomes more complex, then more components will be required and a longer programming string, L, is required. We develop equations for the size of the population, n, and the number of generations required for the population to converge, based on L. Our analytical results show that even though the design search space grows as 2L (assuming a binary programming string), the number of circuit evaluations, n*ngen, only grows as O(Lg3), or slightly less than O(L). This makes evolvable techniques a good tool for exploring large design spaces. The major hurdle for intrinsic EHW is evaluation time for each possible circuit. The evaluation time involves downloading the bit string to the device, updating the device configuration, measuring the output and then transferring the output data to the control processor. Each of these steps must be done for each member of the population. The processing time of the computer becomes negligible since the selection/crossover/mutation steps are only done once per generation. Evaluation time presently limits intrinsic evolvable hardware techniques to designing only small or medium-sized circuits. To evolve large or complicated circuits, several researchers have proposed using hierarchical design or reuse techniques where submodules are combined together to form complex circuits. However, these practical approaches limit the search space of available designs and preclude utilizing parasitic coupling or other effects within the programmable device. The practical approaches also raise the issue of why intrinsic EHW techniques do not easily apply to large design spaces, since the analytical results show only an O(L) complexity growth.

Hereford, James↗
NASA NTRS2000

Displacement Damage in Bipolar Linear Integrated Circuits

Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

Rax, B. G.↗