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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

MacLeod, Todd C.↗
NASA NTRS2014

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

radiation hardened by design↗
DOE OSTI2021

Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology

This paper reports the design and process flow for monolithic integration of lateral high voltage (HV) power MOSFET with low voltage (LV) CMOS circuits for SiC Power IC technology. The reported devices and circuits are fabricated on a N-/N+ 4H-SiC substrate at 150mm, production grade- Analog Devices Inc. (ADI) Hillview fabrication facility located in San Jose. Here, the static performance characteristics of HV NMOS and LV CMOS are reported. For future high temperature applications, the static performances are fully characterized and are reported up to 200oC. Finally, to validate the fabricated CMOS, a 5-stage ring oscillator is also demonstrated.

4H-SiC↗
NASA NTRS1986

Verification of a SEU model for advanced 1-micron CMOS structures using heavy ions

Modeling and test results are reported for 1 micron CMOS circuits. Analytical predictions are correlated with experimental data, and sensitivities to process and design variations are discussed. Unique features involved in predicting the SEU performance of these devices are described. The results show that the critical charge for upset exhibits a strong dependence on pulse width for very fast devices, and upset predictions must factor in the pulse shape. Acceptable SEU error rates can be achieved for a 1 micron bulk CMOS process. A thin retrograde well provides complete SEU immunity for N channel hits at normal incidence angle. Source interconnect resistance can be important parameter in determining upset rates, and Cf-252 testing can be a valuable tool for cost-effective SEU testing.

Cable, J. S.↗
DOE OSTI2024

CMOS photonic integrated circuit for flex-grid polarization entanglement

We showcase a CMOS-fabricated silicon photonic integrated circuit employing a bidirectionally pumped microring and polarization splitter-rotators for high-fidelity polarization entanglement. Spanning the optical C+L-band, this source is ideal for wavelength-multiplexed entanglement distribution in multi-user networks.

Miloshevsky, Alex↗
DOE OSTI2024

Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads

Abstract This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate machine learning (ML) workloads. We conducted an exploration of device fabrication and proposed system-algorithm co-design to boost performance. A novel FeCap device, incorporating an interfacial layer (IL) and$$\text {Hf}_{0.5}\text {Zr}_{0.5}\text {O}_2$$ Hf 0.5 Zr 0.5 O 2 (HZO), ensures a reduction in operating voltage and enhances HZO scaling while being compatible with CMOS circuits. The IL also enriches ferroelectricity and retention properties. When integrated into crossbar arrays, FeCaps and FeFETs demonstrate their effectiveness as IMC components, eliminating sneak paths and enabling selector-less operation, leading to notable improvements in energy efficiency and area utilization. However, it is worth noting that limited capacitance ratios in FeCaps introduced errors in multiply-and-accumulate (MAC) computations. The proposed co-design approach helps in mitigating these errors and achieves high accuracy in classifying the CIFAR-10 dataset, elevating it from a baseline of 10% to 81.7%. FeFETs in crossbars, with a higher on-off ratio, outperform FeCaps, and our proposed charge-based sensing scheme achieved at least an order of magnitude reduction in power consumption, compared to prevalent current-based methods.

Science & Technology - Other Topics↗
DOE OSTI2011

Cold Electronics for Giant Liquid Argon Time Projection Chambers

The choice between cold and warm electronics (inside or outside the cryostat) in very large LAr TPCs (>5-10 ktons) is not an electronics issue, but it is rather a major cryostat design issue. This is because the location of the signal processing electronics has a direct and far reaching effect on the cryostat design, an indirect effect on the TPC electrode design (sense wire spacing, wire length and drift distance), and a significant effect on the TPC performance. All these factors weigh so overwhelmingly in favor of the cold electronics that it remains an optimal solution for very large TPCs. In this paper signal and noise considerations are summarized, the concept of the readout chain is described, and the guidelines for design of CMOS circuits for operation in liquid argon (at {approx}89 K) are discussed.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1981

Development of design, qualification, screening, and application requirements for plastic encapsulated solid-state devices for space applications

Test data were collected on 1035 plastic encapsulated devices and 75 hermetically scaled control group devices that were purchased from each of five different manufacturers in the categories of (1) low power Schottsky TTL (bipolar) digital circuits; (2) CMOS digital circuits; (3) operational amplifier linear circuits; and (4) NPN transistors. These parts were subjected to three different initial screening conditions, then to extended life testing, to determine any possible advantages or trends for any particular screen. Several tests were carried out in the areas of flammability testing, humidity testing, high pressure steam (auroclave) testing, and high temperature storage testing. Test results are presented. Procurement and application considerations for use of plastic encapsulated semiconductors are presented and a statistical analysis program written to study the log normal distributions resulting from life testing is concluded.

Source record↗
NASA NTRS1989

Relationship Between Latchup And Transistor Current Gain

Theoretical study takes new look at current-vs.-voltage behavior of silicon controlled rectifiers (SCR's), four-layer complementary metal oxide/semiconductor (CMOS) devices, and similar devices susceptible to latchup. For purposes of analysis, "latchup" denotes transition of such device from lower-current-conducting steady state to distinct higher-current-conducting steady state. Focuses upon conventional two-couple-transistor model of one-dimensional SCR. Although model gives oversimplified view of latchup in CMOS circuits, useful for qualitative predictions of electrical characteristics.

Edmonds, Larry D.↗
NASA NTRS1992

Unfulfilled needs in IR astronomy focal-plane readout electronics

The NOAO's 8-m IR optimized telescope for Mauna Kea and NASA's SIRTF show that from 1 to 200 microns there are a number of unfulfilled needs in readout electronics. These include: extremely low readnoise, less than 10 electrons, stable operation at temperatures as low as 2 K, high well capacity, greater than 1 e 7 electrons, and integration times from 30 msec to over 100 sec. Sensors for adaptive optics systems are required with readnoise less than 10 electrons and response times of 30 msec. They should be highly efficient from 1 to 2.5 microns, but may have small formats. Ground-based imagers at these wavelengths need comparable readnoise but longer integration times, and the largest possible formats are essential. To achieve these goals improved cryogenic MOSFETS are essential and complete cryogenic CMOS circuits are highly desirable. Experimental cryoptimized MFETS promise to exceed the above noise requirements at 77 K and approach the needs at 2 K.

Low, Frank J.↗
NASA NTRS2003

Radiation tolerant back biased CMOS VLSI

A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

Maki, Gary K.↗
NASA NTRS2008

Nano-Multiplication-Region Avalanche Photodiodes and Arrays

Nano-multiplication-region avalanche photodiodes (NAPDs), and imaging arrays of NAPDs integrated with complementary metal oxide/semiconductor (CMOS) active-pixel-sensor integrated circuitry, are being developed for applications in which there are requirements for high-sensitivity (including photoncounting) detection and imaging at wavelengths from about 250 to 950 nm. With respect to sensitivity and to such other characteristics as speed, geometric array format, radiation hardness, power demand of associated circuitry, size, weight, and robustness, NAPDs and arrays thereof are expected to be superior to prior photodetectors and arrays including CMOS active-pixel sensors (APSs), charge-coupled devices (CCDs), traditional APDs, and microchannelplate/ CCD combinations. Figure 1 depicts a conceptual NAPD array, integrated with APS circuitry, fabricated on a thick silicon-on-insulator wafer (SOI). Figure 2 presents selected aspects of the structure of a typical single pixel, which would include a metal oxide/semiconductor field-effect transistor (MOSFET) integrated with the NAPD. The NAPDs would reside in silicon islands formed on the buried oxide (BOX) layer of the SOI wafer. The silicon islands would be surrounded by oxide-filled insulation trenches, which, together with the BOX layer, would constitute an oxide embedding structure. There would be two kinds of silicon islands: NAPD islands for the NAPDs and MOSFET islands for in-pixel and global CMOS circuits. Typically, the silicon islands would be made between 5 and 10 m thick, but, if necessary, the thickness could be chosen outside this range. The side walls of the silicon islands would be heavily doped with electron-acceptor impurities (p+-doped) to form anodes for the photodiodes and guard layers for the MOSFETs. A nanoscale reach-through structure at the front (top in the figures) central position of each NAPD island would contain the APD multiplication region. Typically, the reach-through structure would be about 0.1 microns in diameter and between 0.3 and 0.4 nm high. The top layer in the reach-through structure would be heavily doped with electron-donor impurities (n+-doped) to make it act as a cathode. A layer beneath the cathode, between 0.1 and 0.2 nm thick, would be p-doped to a concentration .10(exp 17)cu cm. A thin n+-doped polysilicon pad would be formed on the top of the cathode to protect the cathode against erosion during a metal-silicon alloying step that would be part of the process of fabricating the array.

Zheng, Xinyu↗
NASA NTRS2009

Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

Buchner, S.↗
NASA NTRS1977

A complementary MOS process

The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated circuits is described. The fixed-gate array concept is presented as a means of obtaining CMOS integrated circuits in a fast and reliable fashion. Examples of CMOS circuits fabricated by both the conventional method and the fixed-gate array method are included. The electrical parameter specifications and characteristics are given along with typical values used to produce CMOS circuits. Temperature-bias stressing data illustrating the thermal stability of devices manufactured by this process are presented. Results of a preliminary study on the radiation sensitivity of circuits manufactured by this process are discussed. Some process modifications are given which have improved the radiation hardness of our CMOS devices. A formula description of the chemicals and gases along with the gas flow rates is also included.

Jhabvala, M. D.↗
DOE OSTI2025

Gigahertz-frequency acousto-optic phase modulation of visible light in a CMOS-fabricated photonic circuit

Optical phase modulators operating at visible wavelengths are essential components for photonic technologies such as those for quantum control, communications, and laser ranging. However, they remain challenging to implement in scalable, integrated platforms capable of handling high optical powers. Here we present a visible-light, gigahertz-frequency acousto-optic phase modulator, fabricated on a 200-mm wafer in a volume CMOS foundry, that supports greater than 500 mW of optical power at 730 nm. The device combines a piezoelectric transducer and a photonic waveguide within a single, wavelength-scale structure that confines both a propagating optical mode and an electrically excitable breathing-mode mechanical resonance. By tuning the device’s geometry to optimize the optomechanical interaction, we achieve modulation depths up to 4.85 rad with 80 mW of applied microwave power at 2.31 GHz in a 2-mm-long device. This corresponds to resonant modulation figures of merit of V π = 1.32V and V π ⋅ L = 0.26V cm. To our knowledge, this is the lowest V π ever demonstrated in any acousto-optic phase modulator and represents a 15-fold reduction in V π and a 100-fold reduction in required microwave power relative to state-of-the-art modulators with high visible-wavelength power handling commonly employed in quantum control systems.

Freedman, Jacob M. [Univ. of Arizona, Tucson, AZ (↗
DOE OSTI2021

Design of microwave broadband CMOS transmitter and receiver circuits for MIR and ECEI plasma diagnostics

To efficiently determine the plasma electron density fluctuations using the MIR diagnostic technique, a 55–75 GHz 65 nm-CMOS transmitter has been developed where four separate intermediate frequency (IF) signals are up-converted, amplified, and then combined to generate an 8-tone RF output; a broadband 90 nm-CMOS receiver has also been constructed, which consists of an RF-low noise amplifier (LNA), mixer, and IF amplifier. The circuits and their corresponding modules will soon be deployed on the DIII-D and NSTX-U fusion devices. A 110–140 GHz 65 nm-CMOS receiver has also been designed, which is suitable for measuring the deep-core temperature fluctuations in the DIII-D tokamak using the electron cyclotron emission imaging diagnostic system. In addition to the RF-LNA/balun, mixer, and IF amplifier, an LO balun/tripler and driving amplifier are now included in this highly integrated circuit chip. By adopting the microwave and millimeterwave system-on-chip concept in the front-end system design, this paper demonstrates that compact transmitter and receiver modules can be easily built, which, in turn, facilitates array implementation and maintenance.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗