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A JPL-led chip scale package (CSP) Consortium of enterprises, composed of representing agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
Abstract Purpose Intraoperative detection and removal of microscopic residual disease (MRD) remain critical to the outcome of cancer surgeries. Today’s minimally invasive surgical procedures require miniaturization and surgical integration of highly sensitive imagers to seamlessly integrate into the modern clinical workflow. However, current intraoperative imagers remain cumbersome and still heavily dependent on large lenses and rigid filters, precluding further miniaturization and integration into surgical tools. Procedures We have successfully engineered a chip-scale intraoperative micro-imager array—without optical filters or lenses—integrated with lanthanide-based alloyed upconverting nanoparticles (aUCNPs) to achieve tissue imaging using a single micro-chip. This imaging platform is able to leverage the unique optical properties of aUCNPs (long luminescent lifetime, high-efficiency upconversion, no photobleaching) by utilizing a time-resolved imaging method to acquire images using a 36-by-80-pixel, 2.3 mm $$\times$$ × 4.8 mm silicon-based electronic imager micro-chip, that is, less than 100-µm thin. Each pixel incorporates a novel architecture enabling automated background measurement and cancellation. We have validated the performance, spatial resolution, and the background cancellation scheme of the imaging platform, using resolution test targets and mouse prostate tumor sample intratumorally injected with aUCNPs. To demonstrate the ability to image MRD, or tumor margins, we evaluated the imaging platform in visualizing a single-cell thin section of the injected prostate tumor sample. Results Tested on USAF resolution targets, the imager is able to achieve a resolution of 71 µm. We have also demonstrated successful background cancellation, achieving a signal-to-background ratio of 8 when performing ex vivo imaging on aUCNP-injected prostate tumor sample, improved from originally 0.4. The performance of the imaging platform on single-cell layer sections was also evaluated and the sensor achieved a signal-to-background ratio of 4.3 in resolving cell clusters with sizes as low as 200 cells. Conclusion The imaging system proposed here is a scalable chip-scale ultra-thin alternative for bulky conventional intraoperative imagers. Its novel pixel architecture and background correction scheme enable visualization of microscopic-scale residual disease while remaining completely free of lenses and filters, achieving an ultra-miniaturized form factor—critical for intraoperative settings.
Arrays of electrodes integrated with chip-scale packages and silicon-based integrated circuits have been proposed for use as medical electronic implants, including neuro-prosthetic devices that might be implanted in brains of patients who suffer from strokes, spinal-cord injuries, or amyotrophic lateral sclerosis. The electrodes of such a device would pick up signals from neurons in the cerebral cortex, and the integrated circuit would perform acquisition and preprocessing of signal data. The output of the integrated circuit could be used to generate, for example, commands for a robotic arm. Electrode arrays capable of acquiring electrical signals from neurons already exist, but heretofore, there has been no convenient means to integrate these arrays with integrated-circuit chips. Such integration is needed in order to eliminate the need for the extensive cabling now used to pass neural signals to data-acquisition and -processing equipment outside the body. The proposed integration would enable progress toward neuro-prostheses that would be less restrictive of patients mobility. An array of electrodes would comprise a set of thin wires of suitable length and composition protruding from and supported by a fine-pitch micro-ball grid array or chip-scale package (see figure). The associated integrated circuit would be mounted on the package face opposite the probe face, using the solder bumps (the balls of the ball grid array) to make the electrical connections between the probes and the input terminals of the integrated circuit. The key innovation is the insertion of probe wires of the appropriate length and material into the solder bumps through a reflow process, thereby fixing the probes in place and electrically connecting them with the integrated circuit. The probes could be tailored to any distribution of lengths and made of any suitable metal that could be drawn into fine wires. Furthermore, the wires could be coated with an insulating layer using anodization or other processes, to achieve the correct electrical impedance. The probe wires and the packaging materials must be biocompatible using such materials as lead-free solders. For protection, the chip and package can be coated with parylene.
Sensing nitrate concentrations in soil with high sensitivity and selectivity using field-deployable compact sensor platforms is a sought-after goal for environment and agriculture applications. This study demonstrates a new optically based nitrate sensing platform based on ion-selective membrane (ISM) functionalized chip-scale photonic micro-ring resonators. Our approach relies upon measurements of resonance shifts in the micro-resonators and leverages the excellent, though little studied, optical properties of ISMs. Using a high-quality micro-ring resonator, a nitrate ion-selective photonic sensor exhibits a detection limit down to 0.1 parts per million (ppm) and enables nitrate concentration measurements in the 1-100 ppm level, appropriate for soil science and agriculture. Importantly, the sensor also shows high selectivity over other competing anions in soil, such as Cl - and NO 2 - . Here, we argue that this chip-scale approach can be incorporated into compact sensor platforms.
The design, fabrication, and characterization of a 16-element optical phased array (OPA) using a high index (n = 3.1) silicon-rich silicon nitride (SRN) is demonstrated. Here, we present one-dimensional beam steering with end-fire facet antennas over a wide steering range of >115° at a fixed wavelength of 1525 nm. A beam width of 6.3° has been measured at boresight, consistent with theory. We demonstrate SRN as a viable material choice for chip-scale OPA applications due to its high thermo-optic coefficient, high optical power handling capacity [negligible two-photon absorption (TPA)], wide transparency window, and CMOS compatibility.
Microresonator-based soliton generation promises chip-scale integration of optical frequency combs for applications spanning from time keeping to frequency synthesis. Access to the soliton repetition rate is a prerequisite for those applications. While miniaturized cavities harness Kerr nonlinearity and enable terahertz soliton repetition rates, such high rates are not amenable to direct electronic detection. Here, we demonstrate hybrid Kerr and electro-optic microcombs using a lithium niobate thin film that exhibits both Kerr and Pockels nonlinearities. By interleaving the high-repetition-rate Kerr soliton comb with the low-repetition-rate electro-optic comb on the same waveguide, wide Kerr soliton mode spacing is divided within a single chip, allowing for direct electronic detection and feedback control of the soliton repetition rate. Our work establishes an integrated approach to electronically access terahertz solitons, paving the way for building chip-scale referenced comb sources.
This paper reviews the package trend towards further miniaturization of emerging chip scale package (CSP).
Availability of board solder joint reliability information is critical to the wider implementation of Chip Scale Packages (CSPs).
Laser stabilization sits at the heart of many precision scientific experiments and applications, including quantum information science, metrology, and atomic timekeeping. Many of these systems narrow the laser linewidth and stabilize the carrier by use of Pound–Drever–Hall (PDH) locking to a table-scale, ultrahigh quality factor (Q), vacuum spaced Fabry–Perot reference cavity. Integrating these cavities to bring characteristics of PDH stabilization to the chip scale is critical to reducing their size, cost, and weight, and enabling a wide range of portable and system-on-chip applications. We report a significant advance in integrated laser linewidth narrowing, stabilization, and noise reduction by use of a photonic integrated 4.0 m long coil resonator to stabilize a semiconductor laser. We achieve a 36 Hz 1 / π <#comment/> -integral linewidth, Allan deviation of 1.8 × <#comment/> 10 − <#comment/> 13 at 10 ms measurement time, and a 2.3 kHz/s drift—to the best of our knowledge, the lowest integral linewidth and highest stability demonstrated for an integrated waveguide reference cavity. This performance represents over an order of magnitude improvement in integral linewidth and frequency noise over previous integrated waveguide PDH stabilized reference cavities and bulk-optic and integrated injection locked approaches, and over two orders of magnitude improvement in frequency and phase noise than integrated injection locked approaches. Two different wavelength coil designs are demonstrated, stabilizing lasers at 1550 nm and 1319 nm. The resonator is bus-coupled to a 4.0 m long coil, with a 49 MHz free spectral range, mode volume of 1.0 × <#comment/> 10 10 µ <#comment/> m 3 , and 142 million intrinsic Q , fabricated in a CMOS compatible, ultralow loss silicon nitride waveguide platform. Our measurements and simulations show that the thermorefractive noise floor for this particular cavity is reached for frequencies down to 20 Hz in an ambient environment with simple passive vibration isolation and without vacuum or thermal isolation. The thermorefractive noise limited performance is estimated to yield an 8 Hz 1 / π <#comment/> -integral linewidth and Allan deviation of 5 × <#comment/> 10 − <#comment/> 14 at 10 ms, opening a stability regime that heretofore has been available only in fundamentally non-integrated systems. These results demonstrate the potential to bring the characteristics of laboratory-scale stabilized lasers to the integrated, wafer-scale compatible chip scale, and are of interest for a number of applications in quantum technologies and atomic, molecular, and optical physics, and with further developments below 10 Hz linewidth, can be highly relevant to ultralow noise microwave generation.
Optical delay lines control the flow of light in time, introducing phase and group delays for engineering interferences and ultrashort pulses. Photonic integration of such optical delay lines is essential for chip-scale lightwave signal processing and pulse control. However, typical photonic delay lines based on long spiral waveguides require extensively large chip footprints, ranging from mm 2 to cm 2 scales. Here we present a scalable, high-density integrated delay line using a skin-depth engineered subwavelength grating waveguide, i.e., an extreme skin-depth (eskid) waveguide. The eskid waveguide suppresses the crosstalk between closely spaced waveguides, significantly saving the chip footprint area. Our eskid-based photonic delay line is easily scalable by increasing the number of turns and should improve the photonic chip integration density.
The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
Reviews the many factors that affect interconnect reliability of emerging chip scale package (CSP) assemblies. These include: package type, package build, board design, and assembly variables.
Different aspects of advanced surface mount package technology have been investigated. Three key areas included the assembly reliability of conventional Surface Mount (SM), Ball Grid Arrays (BGAs), and Chip Scale Packages (CSPs).
Team members representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
The JPL-led CSP Consortium of enterprises representing government agencies and private companies has jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
The test results for numerous chip scale package assembly performed under MicrotypeBGA Consortium led by the Jet Propulsion Laboratory have been published previously.
The JPL-led CSP Consortium of enterprises representing government agencies and private companies has joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
Key to the design of spacecraft for exploration of the outer planets will be the development of highly integrated and mass/volume efficient electronic systems. Exploration of the outer planets will require optimized propulsion approaches which mandates mass minimization. If one looks at a mission such as the Europa Lander, a high mass/volume efficiency feeds back directly into lower mass for radiation shielding. Concurrently the long mission lengths will drive the need for fault isolation and fault tolerance. The ability to build distributed electronic systems is an inherent requirement and one which is enabled by heterogeneous integration. The electronic packaging approach must be capable of interconnecting various components at a scale comparable with that on the components themselves (chip scale) and it must facilitate efficient integration of the electronics with elements of the spacecraft such as structure or antennae. The concept of 'Heterogeneous Integration' is being explored in the System On A Chip (SOAC) Project at JPL. The goal, of this approach to electronic packaging, is to enable the fabrication and assembly of complete electronic subsystems from components fabricated by a range of processes. Included in such a system could be MEMS sensors, SOI mixed signal ASICs, micro scale passive components and micro power. Secondarily the compact size will enable distributed architectures and integrated assemblies. Additional information is contained in the original extended abstract.