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Three wafering demonstration runs were completed on the Yasunaga wire saw. Wafer thickness/taper uniformity is excellent. Many small problems were encountered with Yasunaga accessories, slowing the effort. A wafer characterization cycle was defined and will be initiated during the next period.
Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.
A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.
A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.
The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.
A reproducible process is described for growing a thick single-crystal layer of cubic SiC on a single-crystal Si wafer by chemical vapor deposition. A buffer layer, grown in situ, is used between the cubic SiC and the Si substrate to minimize the effect of lattice mismatch. Layers of up to 34 microns thick and several sq cm in area have been grown. Wafers are obtained by chemically removing the Si substrates from the grown layers. Excellent electron channeling patterns produced by these wafers indicate very good crystal quality. Preliminary electrical measurements have yielded electron mobilities up to 380 sq cm/Vs.
Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.
Leakage rates of an innovative hypersonic engine seal were measured using a specially developed static high temperature seal test fixture at NASA Lewis Research Center. The three foot long structural panel-edge seal is designed to minimize leakage of high temperature, high pressure gases past the movable panels of advanced ramjet/scramjet engines. The seal is made of a stack of precision machined ceramic wafer pieces that are inserted into a closely conforming seal channel in the movable engine panel. The wafer seal accommodates the significant distortions in the adjacent engine walls through relative sliding between adjacent wafers. Seal leakage rates are presented for engine simulated air temperatures up to 1350 F and for engine pressures up to 100 psi. Leakage rates are also presented for the seal, sealing both a flat wall condition, and an engine simulated distorted wall condition in which the distortion was 0.15 in. in only an 18 in. span. Seal leakage rates were low, meeting an industry-established tentative leakage limit for all combinations of temperature, pressure, and wall conditions considered. Comparisons are made between the measured leakage rates and leakage rates predicted using a seal leakage model developed from externally-pressurized gas film bearing theory.
This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.
A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.
Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.
We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.
We have jointly developed the capability to perform on-wafer s-parameter and noise figure measurements through 220 GHz. S-parameter test sets have been developed covering full waveguide bands of 90-140 GHz (WR-08) and 140-220 GHz (WR-05). The test sets have been integrated with coplanar probes to allow accurate measurements on-wafer. We present the design and performance of the test sets and wafer probes. We also present calibration data as well as measurements of active circuits at frequencies as high as 215 GHz.
Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.
Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.
On September 29, 2017 the Defense Logistics Agency (DLA), Land and Maritime, announced that on September 1, 2017 they had begun a moratorium on the auditing of wafer fabrication facilities (fabs) used in the production of semiconductor die for military (MIL) qualified integrated circuits and discrete semiconductors (transistors and diodes). The announcement said the moratorium would last for six months initially and would apply to all wafer fabs qualified to MIL-PRF-19500 (discretes) and MIL-PRF-38535 (ICs) located, onshore or offshore. The stated rationale behind this action was to give DLA time to evaluate the risk of modifying current surveillance practices across 70+ Federal Stock Classes (FSC) under the jurisdiction of the DLA Qualifying Activity (VQ). The objective was to free up the resources used in these audits so they could be redirected towards audits of other commodities which were under resourced, notably connectors. In the announcement letter, DLA-VQ requested data from the community to assist with decisions on wafer fab re-audit cycle modifications. NASA used available information on current and historical audit schedules to gather such data and analyzed it to provide an in-depth understanding of the impact of locations, part types, in-house or out-of-house fabs on those schedules over time. This presentation provides the results of NASA's data analysis and suggest some changes to auditing practices that could increase efficient use of resources without significant increases in risk.
2D materials, particularly transition metal dichalcogenides (TMDCs), have shown great potential for microelectronics and optoelectronics. However, a major challenge in commercializing these materials is the inability to control their doping at a wafer scale with high spatial fidelity. Interface chemistry is used with the underlying substrate oxide and concomitant exposure to visible light in ambient conditions for photo-dedoping wafer scale MoS 2 . It is hypothesized that the oxide layer traps photoexcited holes, leaving behind long-lived electrons that become available for surface reactions with ambient air at sulfur vacancies (defect sites) resulting in dedoping. Additionally, high fidelity spatial control is showcased over the dedoping process, by laser writing, and fine control achieved over the degree of doping by modulating the illumination time and power density. This localized change in MoS 2 doping density is very stable (at least 7 days) and robust to processing conditions like high temperature and vacuum. The scalability and ease of implementation of this approach can address one of the major issues preventing the “Lab to Fab” transition of 2D materials and facilitate its seamless integration for commercial applications in multi-logic devices, inverters, and other optoelectronic devices.
For the construction of the ATLAS Inner Tracker strip detector, silicon strip sensor modules are glued directly onto carbon fibre support structures using a soft silicone gel. During tests at temperatures below -35°C, several of the sensors were found to crack due to a mismatch in coefficients of thermal expansion between polyimide circuit boards with copper metal layers (glued onto the sensor) and the silicon sensor itself. While module assembly procedures were developed to minimise variations between modules, cold tests showed a wide range of temperatures at which supposedly comparable modules failed. The observed variance (fracture temperatures between -35°C and -70°C) for supposedly comparable modules suggests an undetected variation between modules suspected to be intrinsic to the silicon wafer itself. Therefore, a test programme was developed to investigate the fracture stress of representative sensor wafer cutoffs. This paper presents results for the fracture stress of silicon sensors used in detector modules.