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At least 55 records · Page 3

Setup and Testing of PSEC5 ASIC Boards

The PSEC5 ASIC is a high-speed waveform sampling chip developed for precise measurements. This report presents the design review, test board configurations, and results from functional validation of the PSEC5 device. Key aspects examined include power integrity, voltage-controlled oscillator (VCO) behavior, SPI register functionality, clock division characteristics, readout performance, and analog biasing response. Tests were conducted across two boards under varied voltage conditions and signal configurations. Notable observations include robust VCO output, SPI communication irregularities, and anomalous readout conditions. The findings support design iterations for improved ASIC operability and firmware integration.

Fahey, Alexander [North Central Coll.]↗

An integer- N frequency synthesizer for flexible on-chip clock generation

A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in a 65 nm CMOS process. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked to a 10–50 MHz reference input. The design uses a phase-locked loop (PLL) with a dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, and dual output dividers. The total power consumption from 1.2 V and 0.8 V supplies is 4.0 mW. In conclusion, experimental results confirm the functionality of the proposed synthesizer over a wide range of output frequencies.

47 OTHER INSTRUMENTATION↗

Physical Testing of The PSEC5 ASIC

The PSEC5 ASIC is a high-speed waveform sampling chip designed for ultra-fast timing detectors, offering up to 40 GSPS sampling with 10-bit resolution. This makes it well-suited for applications requiring fine time resolution, such as MCPs and LGADs. This work focuses on the physical testing and validation of the chip s internal clocking and SPI-controlled registers. Testing began with inspection of schematics and the prototype to identify and resolve design issues. Then, custom firmware was developed for an Arduino controller to interface with the chip via SPI, enabling read and write access to key control registers. Results confirm that the VCO operates between ~3.2 4.0 GHz and remains stable under non-VCOVDD fluctuations. The Division Ratio register enables frequency division by known factors (256, 128, 64, etc.), indicating a pre-division frequency of 3.2 GHz when the digital band is unmodified. While most registers responded correctly, some issues were observed, including unexpected current draw and unstable discriminator behavior. Overall, the chip shows promising functionality, but further work is needed to understand the state of the read only registers and address the existing issues. Continued testing and firmware development will be critical to ensuring reliable integration into detector systems.

Fahey, Alexander [Unlisted, US]↗

Portable low-frequency vibration measuring and recording system

Information gathering system measures and records vibrations which affect personnel comfort in space, air, and surface vehicles. Three vibration transducers with mutually perpendicular axes control the frequency output of voltage controlled oscillators /VCO/. Outputs of VCO'S are multiplexed and then recorded on one track of stereo tape recorder.

Clevenson, S. A.↗

FM oscillator has improved deviation linearity

Device can be obtained by driving basic circuit through nonlinear FET input stage. Frequency of VCO is linearized with FET and total variance is varactor controlled. Experimental device exhibited linearity of better than plus or minus one percent for total frequency of plus or minus 10 millihertz.

Honnell, M. A.↗

Automatic communication signal monitoring system

A system is presented for automatic monitoring of a communication signal in the RF or IF spectrum utilizing a superheterodyne receiver technique with a VCO to select and sweep the frequency band of interest. A first memory is used to store one band sweep as a reference for continual comparison with subsequent band sweeps. Any deviation of a subsequent band sweep by more than a predetermined tolerance level produces an alarm signal which causes the band sweep data temporarily stored in one of two buffer memories to be transferred to long-term store while the other buffer memory is switched to its store mode to assume the task of temporarily storing subsequent band sweeps.

Bernstein, A. J.↗

Some effects of quantization on a noiseless phase-locked loop

If the VCO of a phase-locked receiver is to be replaced by a digitally programmed synthesizer, the phase error signal must be sampled and quantized. Effects of quantizing after the loop filter (frequency quantization) or before (phase error quantization) are investigated. Constant Doppler or Doppler rate noiseless inputs are assumed. The main result gives the phase jitter due to frequency quantization for a Doppler-rate input. By itself, however, frequency quantization is impractical because it makes the loop dynamic range too small.

Greenhall, C. A.↗

Internal noise of a phase-locked receiver with a loop-controlled synthesizer

A local oscillator design that uses a digitally programmed frequency synthesizer instead of an analog VCO was proposed. The integral of the synthesizer input, the digital phase, is a convenient measure of integrated Doppler. The internal noise of such a receiver was examined. At high carrier margin, the local oscillator phase noise equals that of the Block IV receiver, about 2 deg rms at S-band, whereas the digital phase noise is about 0.5 deg rms.

Greenhall, C. A.↗

Pulsed Phase-Locked-Loop Strain Monitor

P2sup.L2sup. strain monitor measures strain by monitoring change in phase of acoustic signal that passes through stressed sample. Phase sample causes shift in frequency of VCO. As with other monitors of this type, instrument is only accurate in elastic range of material. Monitor is expected to have broad application in materials testing, structural design, fabrication and assembly.

Heyman, J. S.↗

An update of nonstandard payload modulation restrictions

An upgrade to restrictions as a result of a change of philosophy toward PI receiver false lock avoidance is discussed. This changed philosophy concerns sweeping the receiver VCO sufficiently fast that sideband lock is precluded, rather than relying on the lock detector to discriminate between true lock and false lock signal conditions.

Source record↗

Data acquisition system for NASA LaRC impact dynamics research facility

A data system is designed to permit the simultaneous recording of 90 data channels on one 28 track magnetic tape recorder using a constant bandwidth FM multiplexing technique. Dynamic signals from transducers located in the test aircraft are amplified and fed to voltage controlled oscillators where they are converted to discrete FM signals. The signals from each group of five VCO's are fed to a mixer/distribution amplifier where they are combined into one composite signal and recorded, using direct recording techniques, on one magnetic tape recorder track. Millivolt signals from the recorders reproduce heads are amplified to one volt and then electronically switched to an FM demultiplexing system where appropriate frequency discrimination and signal filtering recover the original analog information.

Mccormick, R. F.↗

60-GHz integrated-circuit high data rate quadriphase shift keying exciter and modulator

An integrated-circuit quadriphase shift keying (QPSK) exciter and modulator have demonstrated excellent performance directly modulating a carrier frequency of 60 GHz with an output phase error of less than 3 degrees and maximum amplitude error of 0.5 dB. The circuit consists of a 60-GHz Gunn VCO phase-locked to a low-frequency reference source, a 4th subharmonic mixer, and a QPSK modlator packaged into a small volume of 1.8 x 2.5 x 0.35 in. The use of microstrip has the advantages of small size, light-weight, and low-cost fabrication. The unit has the potential for multigigabit data rate applications.

Grote, A.↗

False lock in quadriphase receivers with unequal I- and Q-channel data rates

Results are presented concerning the noise-free false-lock problem in quadriphase receivers with unequal I-channel and Q-channel data rates. It is shown that false lock may occur when the incoming carrier frequency and the loop VCO (voltage-controlled oscillator) frequency differ by an amount that is a linear combination of a quarter of I-channel and Q-channel data rates. General expressions for the false-lock performance of quadriphase receivers are given for random as well as periodic data patterns. Specific closed-form expressions for the false-lock margin are are derived when the arm filters of the quadriphase receivers are single-pole Butterworth filters, and the format of the random data is NRZ (nonreturn-to-zero). Numerical evaluations of false-lock margin as a function of the product of 3-dB arm-filter bandwidth and symbol duration are carried out for random data using various arm filters and for different periodic I-chanel and Q-channel data patterns.

Cideciyan, Roy D.↗

Coded 16-CPFSK for downlink applications

A bandwidth-efficient constant-envelope Proof-of-Concept (POC) modem is described. The modem was developed on an Advanced Modulation Techniques Development contract for the NASA/Lewis Research Center. The POC modem employs 16-ary Continuous Phase Frequency Shift Keying (16-CPFSK) modulation. The 16 frequencies are spaced every 1/16th baud rate which produces a compact spectrum allowing 2 bits/sec/Hz operation. The modem is designed for 200 mb/s Time Division Multiple Access (TDMA) application with 100 MHz adjacent channel spacing. Overall rate 3.4 convolutional coding is incorporated. The demodulator differs significantly from typical quadrature phase detector approaches in that phase is coherently measured by processing the baseband output of a frequency discriminator. Baud rate phase samples for the baseband processor are subsequently decoded to yield the original data stream. The method of encoding onto the 16-ary symbol-ending phase nodes, together with convolutional coding gain, results in near Quadrature Phase Shift Keying (QPSK) theoretical performance. The modulated signal is of constant envelope; thus the power amplifier can be saturated for peak performance. The spectrum is inherently bandlimited and requires no RF filter for sidelobe containment. Two novel theoretical techniques are used in this 16-CPFSK modem: (1) coherent phase measurements are obtained by processing an FM discriminator baseband output; and (2) modulation is accomplished via a closed-loop-linearized voltage controlled oscillator (VCO).

Davis, Robert↗

A low-power battery ampere-hour meter

A digital device has been developed to meter the current drain of a battery in ampere hours. The device consists of a voltage controlled oscillator (VCO), a frequency divider, an accumulator, and a liquid crystal display. A voltage proportional to load current is converted into a clock signal whose pulse rate is scaled by the frequency divider to the desired engineering units. Final output pulses are counted and displayed. The use of MOSFET and CMOS integrated circuits allows continuous battery-powered operation over a 3-month time period to an accuracy of +/- 2 percent. The instrument will find application where accurate monitoring of battery charge/discharge status is required over long time intervals.

Tripp, John S.↗

A wide-band fiber optic frequency distribution system employing thermally controlled phase compensation

An active wide-band fiber optic frequency distribution system employing a thermally controlled phase compensator to stabilize phase variations induced by environmental temperature changes is described. The distribution system utilizes bidirectional dual wavelength transmission to provide optical feedback of induced phase variations of 100 MHz signals propagating along the distribution cable. The phase compensation considered differs from earlier narrow-band phase compensation designs in that it uses a thermally controlled fiber delay coil rather than a VCO or phase modulation to compensate for induced phase variations. Two advantages of the wide-band system over earlier designs are (1) that it provides phase compensation for all transmitted frequencies, and (2) the compensation is applied after the optical interface rather than electronically ahead of it as in earlier schemes. Experimental results on the first prototype shows that the thermal stabilizer reduces phase variations and Allan deviation by a factor of forty over an equivalent uncompensated fiber optic distribution system.

Johnson, Dean↗

Improvements to pulsed phase locked loop strain monitor

A pulse phase locked loop system according to the present invention is described. A frequency generator such as a voltage controlled oscillator (VCO) generates an output signal and a reference signal having a frequency equal to that of the output signal. A transmitting gate gates the output frequency signal and this gated signal drives a transmitting transducer which transmits an acoustic wave through a material. A sample/hold samples a signal indicative of the transmitted wave which is received by a receiving transducer. Divide-by-n counters control these gating and sampling functions in response to the reference signal of the frequency generator. Specifically, the output signal is gated at a rate of F/h, wherein F is the frequency of the output signal and h is an integer; and the received signal is sampled at a delay of F/n wherein n is an integer.

Froggatt, Mark E.↗