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At least 55 records · Page 3

A seismic signal processor suitable for use with the NOAA/GOES satellite data collection system

Because of the high data-rate requirements, a practical system capable of collecting seismic information in the field and relaying it, via satellite, to a central collection point is not yet available. A seismic signal processor has been developed and tested for use with the NOAA/GOES satellite data collection system. Performance tests on recorded, as well as real time, short period signals indicate that the event recognition technique used is nearly perfect in its rejection of environmental noise and other non-seismic signals and that, with the use of solid state buffer memories, data can be acquired in many swarm situations. The design of a complete field data collection platform is discussed based on the prototype evaluation.

Webster, W. J., Jr.↗

Reconfigurable Full-Page Braille Displays

Electrically actuated braille display cells of proposed type arrayed together to form full-page braille displays. Like other braille display cells, these provide changeable patterns of bumps driven by digitally recorded text stored on magnetic tapes or in solid-state electronic memories. Proposed cells contain electrorheological fluid. Viscosity of such fluid increases in strong electrostatic field.

Garner, H. Douglas↗

Vertical Bloch Line Storage Technology

Vertical Bloch Line storage is an emerging technology which has the potential for offering a number of desired data storage attributes in a single chip.

Vertical Block Line solid-state memory storage den↗

Space Data Storage Systems and Technologies

A central aspect of most space missions is the acquisition from space of unique mission-specific data and the subsequent return of these data to Earth.

storage ranging from magnetic tape to solid-state ↗

Reversible non-volatile switch based on a TCNQ charge transfer complex

A solid-state synaptic memory matrix (10) having switchable weakly conductive connections at each node (24) whose resistances can be selectably increased or decreased over several orders of magnitude by control signals of opposite polarity, and which will remain stable after the signals are removed, comprises an insulated substrate (16), a set of electrical conductors (14) upon which is deposited a layer (18) of an organic conducting polymer, which changes from an insulator to a conductor upon the transfer of electrons, such as polymerized pyrrole doped with 7,7,8,8-tetracyanoquinodimethane (TCNQ), covered by a second set of conductors (20) laid at right angles to the first.

Nagasubramanian, Ganesan↗

Lunar Reconnaissance Orbiter (LRO) Command and Data Handling Flight Electronics Subsystem

A document describes a high-performance, modular, and state-of-the-art Command and Data Handling (C&DH) system developed for use on the Lunar Reconnaissance Orbiter (LRO) mission. This system implements a complete hardware C&DH subsystem in a single chassis enclosure that includes a processor card, 48 Gbytes of solid-state recorder memory, data buses including MIL-STD-1553B, custom RS-422, SpaceWire, analog collection, switched power services, and interfaces to the Ka-Band and S-Band RF communications systems. The C&DH team capitalized on extensive experience with hardware and software with PCI bus design, SpaceWire networking, Actel FPGA design, digital flight design techniques, and the use of VxWorks for the real-time operating system. The resulting hardware architecture was implemented to meet the LRO mission requirements. The C&DH comprises an enclosure, a backplane, a low-voltage power converter, a single-board computer, a communications interface board, four data storage boards, a housekeeping and digital input/output board, and an analog data acquisition board. The interfaces between the C&DH and the instruments and avionics are connected through a SpaceWire network, a MIL-STD-1553 bus, and a combination of synchronous and asynchronous serial data transfers over RS-422 and LVDS (low-voltage differential-signaling) electrical interfaces. The C&DH acts as the spacecraft data system with an instrument data manager providing all software and internal bus scheduling, ingestion of science data, distribution of commands, and performing science operations in real time.

Nguyen, Quang↗

Coupling of erbium dopants to yttrium orthosilicate photonic crystal cavities for on-chip optical quantum memories

Erbium dopants in crystals exhibit highly coherent optical transitions well suited for solid-state optical quantum memories operating in the telecom band. Here, we demonstrate coupling of erbium dopant ions in yttrium orthosilicate to a photonic crystal cavity fabricated directly in the host crystal using focused ion beam milling. The coupling leads to reduction of the photoluminescence lifetime and enhancement of the optical depth in microns-long devices, which will enable on-chip quantum memories.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Integrated Vertical Bloch Line (VBL) memory

Vertical Bloch Line (VBL) Memory is a recently conceived, integrated, solid state, block access, VLSI memory which offers the potential of 1 Gbit/sq cm areal storage density, data rates of hundreds of megabits/sec, and submillisecond average access time simultaneously at relatively low mass, volume, and power values when compared to alternative technologies. VBLs are micromagnetic structures within magnetic domain walls which can be manipulated using magnetic fields from integrated conductors. The presence or absence of BVL pairs are used to store binary information. At present, efforts are being directed at developing a single chip memory using 25 Mbit/sq cm technology in magnetic garnet material which integrates, at a single operating point, the writing, storage, reading, and amplification functions needed in a memory. The current design architecture, functional elements, and supercomputer simulation results are described which are used to assist the design process.

Katti, R. R.↗

Solid-state Isotopic Power Source for Computer Memory Chips

Recent developments in materials technology now make it possible to fabricate nonthermal thin-film radioisotopic energy converters (REC) with a specific power of 24 W/kg and a 10 year working life at 5 to 10 watts. This creates applications never before possible, such as placing the power supply directly on integrated circuit chips. The efficiency of the REC is about 25 percent which is two to three times greater than the 6 to 8 percent capabilities of current thermoelectric systems. Radio isotopic energy converters have the potential to meet many future space power requirements for a wide variety of applications with less mass, better efficiency, and less total area than other power conversion options. These benefits result in significant dollar savings over the projected mission lifetime.

Brown, Paul M.↗

Systems and methods for rapid processing and storage of data

Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade configured to communicate via a high performance network fabric. In addition, each Solid State Blade includes a processor configured to communicate with a plurality of low power computing complexes interconnected by a router, and each low power computing complex includes at least one general processing core, an accelerator, an I/O interface, and cache memory and is configured to communicate with non-volatile solid state memory.

97 MATHEMATICS AND COMPUTING↗

Systems and methods for rapid processing and storage of data

Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade configured to communicate via a high performance network fabric. In addition, each Solid State Blade includes a processor configured to communicate with a plurality of low power computing complexes interconnected by a router, and each low power computing complex includes at least one general processing core, an accelerator, an I/O interface, and cache memory and is configured to communicate with non-volatile solid state memory.

Stalzer, Mark A.↗

Systems and methods for rapid processing and storage of data

Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade configured to communicate via a high performance network fabric. In addition, each Solid State Blade includes a processor configured to communicate with a plurality of low power computing complexes interconnected by a router, and each low power computing complex includes at least one general processing core, an accelerator, an I/O interface, and cache memory and is configured to communicate with non-volatile solid state memory.

Stalzer, Mark A.↗

A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems

Non-volatile memory (NVM) devices, such as Flash, phase change RAM, spin transfer torque RAM, and resistive RAM, offer several advantages and challenges when compared to conventional memory technologies, such as DRAM and magnetic hard disk drives (HDDs). Here, we present a survey of software techniques that have been proposed to exploit the advantages and mitigate the disadvantages of NVMs when used for designing memory systems, and, in particular, secondary storage (e.g., solid state drive) and main memory. Furthermore, we classify these software techniques along several dimensions to highlight their similarities and differences. Given that NVMs are growing in popularity, we believe that this survey will motivate further research in the field of software technology for NVMs.

97 MATHEMATICS AND COMPUTING↗

Vertical bloch line memory

Vertical Bloch Line (VBL) memory is a recently conceived, integrated, solid-state, block-access, VLSI memory which offers the potential of 1Gbit/sq cm real storage density, gigabit per second data rates, and sub-millisecond average access times simultaneously at relatively low mass, volume, and power values when compared to alternative technologies. VBL's are micromagnetic structures within magnetic domain walls which can be manipulated using magnetic fields from integrated conductors. The presence or absence of VBL pairs are used to store binary information. At present, efforts are being directed at developing a single-chip memory using 25Mbit/sq cm technology in magnetic garnet material which integrates, at a single operating point, the writing, storage, reading, and amplification functions needed in a memory. This paper describes the current design architecture, functional elements, and supercomputer simulation results which are used to assist the design process. The current design architecture uses three metal layers, two ion implantation steps for modulating the thickness of the magnetic layer, one ion implantation step for assisting propagation in the major line track, one NiFe soft magnetic layer, one CoPt hard magnetic layer, and one reflective Cr layer for facilitating magneto-optic observation of magnetic structure. Data are stored in a series of elongated magnetic domains, called stripes, which serve as storage sites for arrays of VBL pairs. The ends of these stripes are placed near conductors which serve as VBL read/write gates. A major line track is present to provide a source and propagation path for magnetic bubbles. Writing and reading, respectively, are achieved by converting magnetic bubbles to VBL's and vice versa. The output function is effected by stretching a magnetic bubble and detecting it magnetoresistively. Experimental results from the past design cycle created four design goals for the current design cycle. First, the bias field ranges for the stripes and the major line needed to be matched. Second, the magnetic field barrier between the stripe and the read/write gates needed to be reduced. Third, current conductor routing needed to be improved to reduce occurrences of open-circuiting, short-circuiting, and eddy-current shielding. Fourth, a modified Co-alloy was needed with an increased coercivity and controlled magnetization to allow VBL stabilization to occur without affecting stripe stability.

Katti, R.↗

Epitaxial Er-doped Y 2 O 3 on silicon for quantum coherent devices

Rare-earth ions have incomplete 4f shells and possess narrow optical intra-4f transitions due to shielding from electrons in the 5s and 5p orbitals, making them good candidates for solid-state optical quantum memory. The emission of Er 3+ in the telecom C-band (1530 nm – 1565 nm) makes it especially attractive for this application. In order to build practical, scalable devices, the REI needs to be embedded in a non-interacting host material, preferably one that can be integrated with silicon. In this paper, we show that Er 3+ can be isovalently incorporated into epitaxial Y 2 O 3 thin films on Si (111). We report on the synthesis of epitaxial, single-crystalline Er:Y 2 O 3 on Si with a narrow inhomogeneous linewidth in the photoluminescence spectra, 5.1 GHz (<100 mK) and an optical excited state lifetime of 8.1 ms. The choice of Y 2 O 3 was driven by its low nuclear spin and small lattice mismatch with Si. Using photoluminescence (PL) and electron paramagnetic resonance, we show that Er 3+ substitutes for Y in the crystal lattice. The role of interfacial SiO x , diffusion of silicon into the film, and the effect of buffer layers on inhomogeneous PL linewidth are examined. We also find that the linewidth decreased monotonically with film thickness but surprisingly exhibits no correlation with the film crystalline quality as measured by the x-ray rocking curve scans suggesting other factors at play that limit the inhomogeneous broadening in Y 2 O 3 films.

36 MATERIALS SCIENCE↗

NAS technical summaries: Numerical aerodynamic simulation program, March 1991 - February 1992

NASA created the Numerical Aerodynamic Simulation (NAS) Program in 1987 to focus resources on solving critical problems in aeroscience and related disciplines by utilizing the power of the most advanced supercomputers available. The NAS Program provides scientists with the necessary computing power to solve today's most demanding computational fluid dynamics problems and serves as a pathfinder in integrating leading-edge supercomputing technologies, thus benefiting other supercomputer centers in Government and industry. This report contains selected scientific results from the 1991-92 NAS Operational Year, March 4, 1991 to March 3, 1992, which is the fifth year of operation. During this year, the scientific community was given access to a Cray-2 and a Cray Y-MP. The Cray-2, the first generation supercomputer, has four processors, 256 megawords of central memory, and a total sustained speed of 250 million floating point operations per second. The Cray Y-MP, the second generation supercomputer, has eight processors and a total sustained speed of one billion floating point operations per second. Additional memory was installed this year, doubling capacity from 128 to 256 megawords of solid-state storage-device memory. Because of its higher performance, the Cray Y-MP delivered approximately 77 percent of the total number of supercomputer hours used during this year.

Source record↗

Manganese oxide microswitch for electronic memory based on neural networks

A solid-state, resistance tailorable, programmable-once, binary, nonvolatile memory switch based on manganese oxide thin films is reported. MnO(x) exhibits irreversible memory switching from conducting (on) to insulating (off) state, with the off and on resistance ratio of greater than 10,000. The switching mechanism is current-triggered chemical transformation of a conductive MnO(2-Delta) to an insulating Mn2O3 state. The energy required for switching is of the order of 4-20 nJ/sq micron. The low switching energy, stability of the on and off states, and tailorability of the on state resistance make these microswitches well suited as programmable binary synapses in electronic associative memories based on neural network models.

Ramesham, R.↗