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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

200 mm sensor development using bonded wafers

Sensors fabricated from high resistivity, float zone, silicon material have been the basis of vertex detectors and trackers for the last 30 years. The areas of these devices have increased from a few square cm to > 200m 2 for the existing CMS tracker. High Luminosity Large Hadron Collider (HL-LHC), CMS and ATLAS tracker upgrades will each require more than 200 m 2 of silicon and the CMS High Granularity Calorimeter (HGCAL) will require more than 600 m 2 . The cost and complexity of assembly of these devices is related to the area of each module, which in turn is set by the size of the silicon sensors. In addition to large area, the devices must be radiation hard, which requires the use of sensors thinned to 200 microns or less. The combination of wafer thinning and large wafer diameter is a significant technical challenge, and is the subject of this work. In this paper we describe work on development of thin sensors on 200 mm wafers using wafer bonding technology. Results of development runs with float zone, Silicon-on-Insulator and Silicon-Silicon bonded wafer technologies are reported.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1984

Recent developments in semiconductor research

Recent findings drawn from various laboratories focused toward a new understanding of the nature of crystal growth and how impurities are incorporated or excluded from the lattice were considered. From these findings a heuristic approach is given for improving the uniformity and charge carrier concentration of thin semiconductor films. Such improvement is considered essential to achieve respectable yield on large scale integrated circuits. A tentative conclusion is drawn which indicates that if the host compound crystal reactants are provided to the growing crystal surface in a reasonably stoichiometric manner, it is virtually impossible to include impurities into a growing crystal surface held at a sufficiently low temperature; impurities are incorporated into the crystal by gettering action of crystal defects located one and two monlayers beneath the growing surface. Devices in 3-5 semiconductors based on heterojunctions and two dimensional electron gases are noted and reliability concerns are voiced. Alternatives and novel device structures such as truly single crystal high quality silicon on insulator and beta silicon carbide devices are presented.

Yoder, M. N.↗
NASA NTRS1999

Waterproof Silicone Coatings of Thermal Insulation and Vaporization Method

Thermal insulation composed of porous ceramic material can be waterproofed by producing a thin silicone film on the surface of the insulation by exposing it to volatile silicone precursors at ambient conditions. When the silicone precursor reactants are multi-functional siloxanes or silanes containing alkenes or alkynes carbon groups higher molecular weight films can be produced. Catalyst are usually required for the silicone precursors to react at room temperature to form the films. The catalyst are particularly useful in the single component system e.g. dimethylethoxysilane (DNMS) to accelerate the reaction and decrease the time to waterproof and protect the insulation. In comparison to other methods, the chemical vapor technique assures better control over the quantity and location of the film being deposited on the ceramic insulation to improve the waterproof coating.

Cagliostro, Domenick E.↗
NASA NTRS1972

Acoustic-wave detection via a piezoelectric field-effect transducer.

An oriented piezoelectric film has been incorporated in the insulator region of a silicon insulated-gate field-effect transistor to provide a sensitive high-frequency strain transducer. With this device, strains as low as 10 to the -8th power have been detected, and gauge factors of roughly 7000 have been attained for applied ac strains at 5.6 MHz.

Greeneich, E. W.↗
NASA NTRS1975

Theoretical transducer properties of piezoelectric insulator FET transducers

An oriented piezoelectric film incorporated in the insulator region of a silicon insulated-gate field-effect transistor (FET) results in a sensitive high-frequency strain transducer. Theory governing the transducer properties of the piezoelectric insulator FET transducer is presented. Equations are developed which relate the drain current of the device to induced polarizations of the piezoelectric layer. The highest frequency of surface strains to which the FET transducer can respond is determined by the FET frequency response - ultimately by the channel transit time. This frequency can extend to the GHz range. The low-frequency response to applied strain is determined by the dielectric relaxation frequency of the piezoelectric layer.

Greeneich, E. W.↗
NASA NTRS2005

Making Wide-IF SIS Mixers with Suspended Metal-Beam Leads

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide-intermediate-frequency-band (wide-IF) superconductor/insulator/superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25- m-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections: 1. The front-side process, in which SIS devices with beam leads are formed on a SOI wafer; 2. The backside process, in which the SOI wafer is wax-mounted onto a carrier wafer, then thinned, then partitioned into individual devices; and 3. The release process, in which the individual devices are separated using a lithographic dicing technique. The total thickness of the starting 4-in. (10.16-cm)-diameter SOI wafer includes 25 m for the Si device layer, 0.5 m for the buried oxide (BOX) layer, and 350 m the for Si-handle layer. The front-side process begins with deposition of an etch-stop layer of SiO2 or AlN(x), followed by deposition of a Nb/Al- AlN(x) /Nb trilayer in a load-locked DC magnetron sputtering system. The lithography for four of a total of five layers is performed in a commercial wafer-stepping apparatus. Diagnostic test dies are patterned concurrently at certain locations on the wafer, alongside the mixer devices, using a different mask set. The conventional, self-aligned lift-off process is used to pattern the SIS devices up to the wire level.

Kaul, Anupama↗
DOE OSTI2024

Solid state protective smart plug device

A wireless-controlled smart plug device and methods of use and operation, using a solid state switch to provide electrical power from an outlet to a load, and provide protection against overload, short circuit, ground, arc, or voltage surge faults. The switch includes a bidirectional semiconductor switch with two back-to-back connected transistors, such as silicon power MOSFETs, silicon insulated-gate bipolar transistors (IGBTs), silicon carbide (SiC) transistors, or gallium nitride (GaN) transistors, each configured to control the current flow from the electrical receptacle to the external electrical load.

Shen, Zheng↗
NASA NTRS1972

Bonding of reusable surface insulation with low density silicone foams

The development and evaluation of a reduced density, high reliable foamed bond strain isolation system for attaching reusable surface insulation to the space shuttle structure are reported. Included are data on virgin materials as well as on materials that received 100 cycles of exposure to 650 F for approximately 20 minutes per cycle. Room temperature vulcanizing silicon elastomers meet all the requirments for an adhesive bonding system.

Hiltz, A. A.↗
NASA NTRS2012

Measurement of Two-Phase Flow and Heat Transfer Parameters using Infrared Thermometry

A novel technique to measure heat transfer and liquid film thickness distributions over relatively large areas for two-phase flow and heat transfer phenomena using infrared (IR)thermometry is described. IR thermometry is an established technology that can be used to measure temperatures when optical access to the surface is available in the wavelengths of interest. In this work, a midwave IR camera (3.6-5.1 microns) is used to determine the temperature distribution within a multilayer consisting of a silicon substrate coated with a thin insulator. Since silicon is largely transparent to IR radiation, the temperature of the inner and outer walls of the multilayer can be measured by coating selected areas with a thin, IR opaque film. If the fluid used is also partially transparent to IR, the flow can be visualized and the liquid film thickness can be measured. The theoretical basis for the technique is given along with a description of the test apparatus and data reduction procedure. The technique is demonstrated by determining the heat transfer coefficient distributions produced by droplet evaporation and flow boiling heat transfer.

Kim, Tae-Hoon↗
NASA NTRS2016

500 C Electronic Packaging and Dielectric Materials for High Temperature Applications

High-temperature environment operable sensors and electronics are required for exploring the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and application of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high temperature electronics, and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by these high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed. High-temperature environment operable sensors and electronics are required for probing the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and eventual applications of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high electronics and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed.

dielectric performance↗
DOE OSTI2024

Tunable quantum emitters on large-scale foundry silicon photonics

Abstract Controlling large-scale many-body quantum systems at the level of single photons and single atomic systems is a central goal in quantum information science and technology. Intensive research and development has propelled foundry-based silicon-on-insulator photonic integrated circuits to a leading platform for large-scale optical control with individual mode programmability. However, integrating atomic quantum systems with single-emitter tunability remains an open challenge. Here, we overcome this barrier through the hybrid integration of multiple InAs/InP microchiplets containing high-brightness infrared semiconductor quantum dot single photon emitters into advanced silicon-on-insulator photonic integrated circuits fabricated in a 300 mm foundry process. With this platform, we achieve single-photon emission via resonance fluorescence and scalable emission wavelength tunability. The combined control of photonic and quantum systems opens the door to programmable quantum information processors manufactured in leading semiconductor foundries.

Larocque, Hugo (ORCID:000900095849780X)↗
NASA NTRS2012

Fabrication of an Absorber-Coupled MKID Detector

Absorber-coupled microwave kinetic inductance detector (MKID) arrays were developed for submillimeter and far-infrared astronomy. These sensors comprise arrays of lambda/2 stepped microwave impedance resonators patterned on a 1.5-mm-thick silicon membrane, which is optimized for optical coupling. The detector elements are supported on a 380-mm-thick micro-machined silicon wafer. The resonators consist of parallel plate aluminum transmission lines coupled to low-impedance Nb microstrip traces of variable length, which set the resonant frequency of each resonator. This allows for multiplexed microwave readout and, consequently, good spatial discrimination between pixels in the array. The transmission lines simultaneously act to absorb optical power and employ an appropriate surface impedance and effective filling fraction. The fabrication techniques demonstrate high-fabrication yield of MKID arrays on large, single-crystal membranes and sub-micron front-to-back alignment of the micro strip circuit. An MKID is a detector that operates upon the principle that a superconducting material s kinetic inductance and surface resistance will change in response to being exposed to radiation with a power density sufficient to break its Cooper pairs. When integrated as part of a resonant circuit, the change in surface impedance will result in a shift in its resonance frequency and a decrease of its quality factor. In this approach, incident power creates quasiparticles inside a superconducting resonator, which is configured to match the impedance of free space in order to absorb the radiation being detected. For this reason MKIDs are attractive for use in large-format focal plane arrays, because they are easily multiplexed in the frequency domain and their fabrication is straightforward. The fabrication process can be summarized in seven steps: (1) Alignment marks are lithographically patterned and etched all the way through a silicon on insulator (SOI) wafer, which consists of a thin silicon membrane bonded to a thick silicon handle wafer. (2) The metal microwave circuitry on the front of the membrane is patterned and etched. (3) The wafer is then temporarily bonded with wafer wax to a Pyrex wafer, with the SOI side abutting the Pyrex. (4) The silicon handle component of the SOI wafer is subsequently etched away so as to expose the membrane backside. (5) The wafer is flipped over, and metal microwave circuitry is patterned and etched on the membrane backside. Furthermore, cuts in the membrane are made so as to define the individual detector array chips. (6) Silicon frames are micromachined and glued to the silicon membrane. (7) The membranes, which are now attached to the frames, are released from the Pyrex wafer via dissolution of the wafer wax in acetone.

Brown, Ari↗
NASA NTRS2003

Ultra-Sensitive Magnetoresistive Displacement Sensing Device

An ultrasensitive displacement sensing device for use in accelerometers, pressure gauges, temperature transducers, and the like, comprises a sputter deposited, multilayer, magnetoresistive field sensor with a variable electrical resistance based on an imposed magnetic field. The device detects displacement by sensing changes in the local magnetic field about the magnetoresistive field sensor caused by the displacement of a hard magnetic film on a movable microstructure. The microstructure, which may be a cantilever, membrane, bridge, or other microelement, moves under the influence of an acceleration a known displacement predicted by the configuration and materials selected, and the resulting change in the electrical resistance of the MR sensor can be used to calculate the displacement. Using a micromachining approach, very thin silicon and silicon nitride membranes are fabricated in one preferred embodiment by means of anisotropic etching of silicon wafers. Other approaches include reactive ion etching of silicon on insulator (SOI), or Low Pressure Chemical Vapor Deposition of silicon nitride films over silicon substrates. The device is found to be improved with the use of giant magnetoresistive elements to detect changes in the local magnetic field.

Olivas, John D.↗
NASA NTRS2016

An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlationare proportional to N2 and dominate at sufficiently large N. Here we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope's bandwidth (the so-called "FX" structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N=32 antennas with 2 opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chipmemory and the CMACs are re-used as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the IC's size and power consumption. It isintended for fabrication in a 32 nm silicon-on-insulator process, where it will require less than 12mm2 of silicon area and achieve an energy efficiency of 1.76 to 3.3 pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to N = 4096. The system-level energy efficiency, including board-levelI/O, power supplies, and controls, is expected to be 5 to 7 pJ per CMAC operation. Existing correlators for the JVLA (N = 32) and ALMA (N = 64) telescopes achieve about 5000 pJ and 1000 pJ respectively usingapplication-specific ICs in older technologies. To our knowledge, the largest-N existing correlator is LEDA atN = 256; it uses GPUs built in 28 nm technology and achieves about 1000 pJ. Correlators being designed for the SKA telescopes (N = 128 and N = 512) using FPGAs in 16nm technology are predicted to achieve about 100 pJ.

ASIC↗
NASA NTRS2018

A First Look at 22 nm FDSOI SRAM Single-Event Test Results

We will present the first ever single-event effects testing results on a 22 nm fully-depleted silicon-on-insulator test chip. The 128 MB SRAMs were irradiated with heavy ions and the results are compared to previous technology generations.

Silicon-on-insulator↗
NASA NTRS2020

Recent Radiation Test Results on a 22FDX Test Vehicle

Total ionizing dose irradiations were performed on a 22 nm fully-depleted silicon-on-insulator static random access memory. There is a strong well-bias effect in the TID response. Combined TID and SEE results are also presented.

total ionizing dose↗