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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

Electrical properties of epitaxial 3C- and 6H-SiC p-n junction diodes produced side-by-side on 6H-SiC substrates

3C-SiC (beta-SiC) and 6H-SiC p-n junction diodes have been fabricated in regions of both 3C-SiC and 6H-SiC epitaxial layers which were grown side-by-side on low-tilt-angle 6H-SiC substrates via a chemical vapor deposition (CVD) process. Several runs of diodes exhibiting state-of-the-art electrical characteristics were produced, and performance characteristics were measured and compared as a function of doping, temperature, and polytype. The first 3C-SiC diodes which rectify to reverse voltages in excess of 300 V were characterized, representing a six-fold blocking voltage improvement over experimental 3C-SiC diodes produced by previous techniques. When placed under sufficient forward bias, the 3C-SiC diodes emit significantly bright green-yellow light while the 6H-SiC diodes emit in the blue-violet. The 6H-SiC p-n junction diodes represent the first reported high-quality 6H-SiC devices to be grown by CVD on very low-tilt-angle (less than 0.5 deg off the (0001) silicon face) 6H substrates. The reverse leakage current of a 200 micron diameter circular device at 1100 V reverse bias was less than 20 nA at room temperature, and excellent rectification characteristics were demonstrated at the peak characterization temperature of 400 C.

EPITAXIAL LAYER↗
NASA NTRS2002

Growth of Defect-Free 3C-Sic on 4H- and 6H-SIC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3C-SiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (Delta/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗
NASA NTRS2011

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Krasowski, Michael J.↗
NASA NTRS2001

Growth of Defect-Free 3C-SiC on 4H- and 6H-SiC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3CSiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (delta a/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗
NASA NTRS1983

Production of large-area single-crystal wafers of cubic SiC for semiconductor devices

A reproducible process is described for growing a thick single-crystal layer of cubic SiC on a single-crystal Si wafer by chemical vapor deposition. A buffer layer, grown in situ, is used between the cubic SiC and the Si substrate to minimize the effect of lattice mismatch. Layers of up to 34 microns thick and several sq cm in area have been grown. Wafers are obtained by chemically removing the Si substrates from the grown layers. Excellent electron channeling patterns produced by these wafers indicate very good crystal quality. Preliminary electrical measurements have yielded electron mobilities up to 380 sq cm/Vs.

Nishino, S.↗
NASA NTRS1996

Silicon Carbide Epitaxial Films Studied by Atomic Force Microscopy

Silicon carbide (SiC) holds great potential as an electronic material because of its wide band gap energy, high breakdown electric field, thermal stability, and resistance to radiation damage. Possible aerospace applications of high-temperature, high-power, or high-radiation SiC electronic devices include sensors, control electronics, and power electronics that can operate at temperatures up to 600 C and beyond. Commercially available SiC devices now include blue light-emitting diodes (LED's) and high-voltage diodes for operation up to 350 C, with other devices under development. At present, morphological defects in epitaxially grown SiC films limit their use in device applications. Research geared toward reducing the number of structural inhomogeneities can benefit from an understanding of the type and nature of problems that cause defects. The Atomic Force Microscope (AFM) has proven to be a useful tool in characterizing defects present on the surface of SiC epitaxial films. The in-house High-Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center not only extended the dopant concentration range achievable in epitaxial SiC films, but it reduced the concentration of some types of defects. Advanced structural characterization using the AFM was warranted to identify the type and structure of the remaining film defects and morphological inhomogeneities. The AFM can give quantitative information on surface topography down to molecular scales. Acquired, in part, in support of the Advanced High Temperature Engine Materials Technology Program (HITEMP), the AFM had been used previously to detect partial fiber debonding in composite material cross sections. Atomic force microscopy examination of epitaxial SiC film surfaces revealed molecular-scale details of some unwanted surface features. Growth pits propagating from defects in the substrate, and hillocks due, presumably, to existing screw dislocations in the substrates, were imaged. Away from local defects, step bunching was observed to yield step heights of hundreds of angstroms, with possible implications for the uniformity of dopants incorporated in SiC devices during fabrication. The quantitative topographic data from the AFM allow the relevant defect information to be extracted, such as the size and distribution of step bunching and the Burgers vector of screw dislocations. These atomic force microscopy results have furthered the understanding of the dynamic epitaxial SiC growth process. A model describing the observed hillock step bunching has been proposed. This cooperation between researchers involved in crystal growth, electronic device fabrication, and surface structural characterization is likely to continue as atomic force microscopy is used to improve SiC films for high-temperature electronic devices for NASA's advanced turbine engines and space power devices, as well as for future applications in the automotive industry.

Source record↗
NASA NTRS1998

Study of Bulk and Elementary Screw Dislocation Assisted Reverse Breakdown in Low-Voltage (less than 250 V) 4H-SiC p(+)n Junction diodes: DC Properties - Part 1

Given the high density (approx. 10(exp 4)/sq cm) of elementary screw dislocations (Burgers vector = 1c with no hollow core) in commercial SiC wafers and epilayers, all appreciable current (greater than 1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the DC-measured reverse-breakdown characteristics of low-voltage (less than 250 V) small-area (less than 5 x 10(exp -4)/sq cm) 4H-SiC p(+)n diodes with and without elementary screw dislocations. Compared to screw dislocation-free devices, diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown I-V knees, and highly localized microplasmic breakdown current filaments. The observed localized 4H-SiC breakdown parallels microplasmic breakdowns observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased.

Neudeck, Philip G.↗
NASA NTRS1999

Study of Bulk and Elementary Screw Dislocation Assisted Reverse Breakdown in Low-Voltage (<250 V) 4H-SiC p+n Junction Diodes - Part 1: DC Properties

Given the high density (approx. 10(exp 4)/sq cm) of elementary screw dislocations (Burgers vector = lc with no hollow core) in commercial SiC wafers and epilayers, all appreciable current (greater than 1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the DC-measured reverse-breakdown characteristics of low-voltage (less than 250 V) small-area (less than 5 x 10(exp -4) sq cm) 4H-SiC p(+)n diodes with and without elementary screw dislocations. Compared to screw dislocation-free devices, diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown I-V knees, and highly localized microplasmic breakdown current filaments. The observed localized 4H-SiC breakdown parallels microplasmic breakdowns observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased.

Neudeck, Philip G.↗
NASA NTRS2001

Thermally Stable Ohmic Contacts on Silicon Carbide Developed for High- Temperature Sensors and Electronics

The NASA aerospace program, in particular, requires breakthrough instrumentation inside the combustion chambers of engines for the purpose of, among other things, improving computational fluid dynamics code validation and active engine behavioral control (combustion, flow, stall, and noise). This environment can be as high as 600 degrees Celsius, which is beyond the capability of silicon and gallium arsenide devices. Silicon-carbide- (SiC-) based devices appear to be the most technologically mature among wide-bandgap semiconductors with the proven capability to function at temperatures above 500 degrees Celsius. However, the contact metalization of SiC degrades severely beyond this temperature because of factors such as the interdiffusion between layers, oxidation of the contact, and compositional and microstructural changes at the metal/semiconductor interface. These mechanisms have been proven to be device killers. Very costly and weight-adding packaging schemes that include vacuum sealing are sometimes adopted as a solution.

Okojie, Robert S.↗
NASA NTRS2003

Silicon Carbide Diodes Performance Characterization and Comparison With Silicon Devices

Commercially available silicon carbide (SiC) Schottky diodes from different manufacturers were electrically tested and characterized at room temperature. Performed electrical tests include steady state forward and reverse I-V curves, as well as switching transient tests performed with the diodes operating in a hard switch dc-to-dc buck converter. The same tests were performed in current state of the art silicon (Si) and gallium arsenide (GaAs) Schottky and pn junction devices for evaluation and comparison purposes. The SiC devices tested have a voltage rating of 200, 300, and 600 V. The comparison parameters are forward voltage drop at rated current, reverse current at rated voltage and peak reverse recovery currents in the dc to dc converter. Test results show that steady state characteristics of the tested SiC devices are not superior to the best available Si Schottky and ultra fast pn junction devices. Transient tests reveal that the tested SiC Schottky devices exhibit superior transient behavior. This is more evident at the 300 and 600 V rating where SiC Schottky devices showed drastically lower reverse recovery currents than Si ultra fast pn diodes of similar rating.

Lebron-Velilla, Ramon C.↗
NASA NTRS2008

Update on Development of SiC Multi-Chip Power Modules

Progress has been made in a continuing effort to develop multi-chip power modules (SiC MCPMs). This effort at an earlier stage was reported in 'SiC Multi-Chip Power Modules as Power-System Building Blocks' (LEW-18008-1), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 28. The following recapitulation of information from the cited prior article is prerequisite to a meaningful summary of the progress made since then: 1) SiC MCPMs are, more specifically, electronic power-supply modules containing multiple silicon carbide power integrated-circuit chips and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking; 2) The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules; and, 3) In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications. Because identical SiC MCPM building blocks could be utilized in such a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. This concludes the information from the cited prior article. The main activity since the previously reported stage of development was the design, fabrication, and testing a 120- VDC-to-28-VDC modular power-converter system composed of eight SiC MCPMs in a 4 (parallel)-by-2 (series) matrix configuration, with normally-off controllable power switches. The SiC MCPM power modules include closed-loop control subsystems and are capable of operating at high power density or high temperature. The system was tested under various configurations, load conditions, load-transient conditions, and failure-recovery conditions. Planned future work includes refinement of the demonstrated modular system concept and development of a new converter hardware topology that would enable sharing of currents without the need for communication among modules. Toward these ends, it is also planned to develop a new converter control algorithm that would provide for improved sharing of current and power under all conditions, and to implement advanced packaging concepts that would enable operation at higher power density.

Lostetter, Alexander↗
NASA NTRS2008

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

Krasowski, Michael J.↗
NASA NTRSDate not supplied

DC Modeling of 4H-SiC JFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460 °C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6μm (for recently fabricated Gen. 11 ICs) limits on mission relevant circuit capabilities [1]. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies to reduce the SiC JFET channel length while maintaining turn-off behavior (Fig. 1a) needed to realize 500 °C circuit operation. The first fabrication strategy uses a shallow self-align nitrogen implant (Figure 1b) along the device's top surface but not below the gate combined with a high-dose phosphorous implant directly below the source and drain contacts. For the second fabrication strategy (Figure 1c), the high-dose phosphorous implants extended from below the contacts all the way up to the gate edges. Simulations guided gate length reductions without significant degradation in the turn-off performance. In total 12 SiC JFET variants implementing using the different fabrication strategies, gate lengths, and n-channel epilayer thickness were implemented in our simulation framework implemented in COMSOL. Since the COMSOL database does not have the material properties for 4H-SiC, these parameters were taken from the literature and implemented in COMSOL. The empirical models [2] for incomplete ionization, Auger recombination, low field mobility, and Shockley-Read-Hall recombination were implemented to account for material-specific device behavior.

4H-SiC JFET↗
NASA NTRSDate not supplied

DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n− and deep n+) to reduce the SiC JFET channel length while maintaining turn-off behavior needed to realize 500 °C circuit operation. First, the material properties for 4H-SiC were implemented in COMSOL and the Poisson equation was solved for twelve 2D device designs. Then, based on the insights gained from the distribution of the electron concentration, electrostatic potential, and electric field for twelve designs (with three fabrication strategies), simulation for a 1 μm gate length nJFET with the turn-off performance comparable to the state-of-the-art.

4H-SiC nJFET↗
NASA NTRSDate not supplied

DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n− and deep n+) to reduce the SiC JFET channel length while maintaining turn-off behavior needed to realize 500 °C circuit operation. First, the material properties for 4H-SiC were implemented in COMSOL and the Poisson equation was solved for twelve 2D device designs. Then, based on the insights gained from the distribution of the electron concentration, electrostatic potential, and electric field for twelve designs (with three fabrication strategies), simulation for a 1 μm gate length nJFET with the turn-off performance comparable to the state-of-the-art.

4H-SiC nJFET↗
NASA NTRS2006

Graded junction termination extensions for electronic devices

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Merrett, J. Neil↗
NASA NTRS2007

Graded junction termination extensions for electronic devices

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Merrett, J. Neil↗