Assessing the reliability of SiC MOSFET through inverter-like accelerated test vs. power cycling test
Not Available
14 SOLAR ENERGY↗
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Gate protection for vertical gallium nitride trench MOSFETs: The buried field shield
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42 ENGINEERING↗
Identification of localized radiation damage in power MOSFETs using EBIC imaging
The rapidly increasing use of electronics in high-radiation environments and the continued evolution in transistor architectures and materials demand improved methods to characterize the potential damaging effects of radiation on device performance. Here, electron-beam-induced current is used to map hot-carrier transport in model metal-oxide semiconductor field-effect transistors irradiated with a 300 KeV focused He + beam as a localized line spanning across the gate and bulk Si. By correlating the damage to the electronic properties and combining these results with simulations, the contribution of spatially localized radiation damage on the device characteristics is obtained. Furthermore, this identified damage, caused by the He + beam, is attributed to localized interfacial P b centers and delocalized positive fixed-charges, as surmised from simulations. Comprehension of the long-term interaction and mobility of radiation-induced damage are key for future design of rad-hard devices.
73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
Optoelectronic and structural characterization of trapezoidal defects in 4H-SiC epilayers and the effect on MOSFET reliability
To this day, trapezoidal defects are found in clusters and high counts in wafers representing the industry standard in terms of material quality being produced. This study sheds light on the nature, origin, behavior, and impact of this defect on device yield and reliability. Trapezoidal defects in 4H-SiC epitaxial layers were investigated by photoluminescence (PL) imaging, scanning electron microscopy (SEM), cathodoluminescence spectrum imaging (CLSI), SEM electron beam induced current (EBIC) imaging, and by transmission electron microscopy (TEM) observation. The bar-shaped stacking faults were identified by the PL and CL measurements with a peak emission wavelength of 420 and 450 nm. An optoelectronic behavioral study based on the recombination enhanced dislocation glide mechanism revealed how expanding dislocations and stacking faults interact with each other. Combining the luminescence and microscopy results, the nature of the stacking faults was identified as being a combination of Shockley-type and Frank-type stacking faults. The TEM analysis showed that these defects originate from the substrate and the stacking sequences of some of the faults were determined as (…2, 4, 2…) and (…2, 3, 2…) in the Zhdanov's notation by high-resolution TEM. The origin of this defect is speculated based on our results and previous reports. The EBIC imaging showed that the high density of SFs in these towers is a strong site of carrier recombination, which presumably has an impact on the transfer characteristics of SiC devices. Furthermore, these defects have shown to impact metal oxide semiconductor field effect transistors electrical performance via an increase in the on-state resistance depending on the coverage percentage of the tower of defects in the active area of the device.
4H-SiC↗
Gate-Driver Integrated Junction Temperature Estimation of SiC MOSFET Modules
Not provided.
Engineering↗
Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K
Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.
circuit modeling↗