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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2000

Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

Asenov, Asen↗
NASA NTRS2000

Random Telegraph Signal Amplitudes in Sub 100 nm (Decanano) MOSFETs: A 3D 'Atomistic' Simulation Study

In this paper we use 3D simulations to study the amplitudes of random telegraph signals (RTS) associated with the trapping of a single carrier in interface states in the channel of sub 100 nm (decanano) MOSFETs. Both simulations using continuous doping charge and random discrete dopants in the active region of the MOSFETs are presented. We have studied the dependence of the RTS amplitudes on the position of the trapped charge in the channel and on the device design parameters. We have observed a significant increase in the maximum RTS amplitude when discrete random dopants are employed in the simulations.

Asenov, Asen↗
NASA NTRS2000

2D Quantum Mechanical Study of Nanoscale MOSFETs

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density-gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. We present the results of our simulations of MIT 25, 50 and 90 nm "well-tempered" MOSFETs and compare them to those of classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. Surprisingly, the self-consistent potential profile shows lower injection barrier in the channel in quantum case. These results are qualitatively consistent with ID Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and subthreshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Svizhenko, Alexei↗
NASA NTRS2001

2D Quantum Transport Modeling in Nanoscale MOSFETs

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density- gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions, oxide tunneling and phase-breaking scattering are treated on equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Quantum simulations are focused on MIT 25, 50 and 90 nm "well- tempered" MOSFETs and compared to classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. These results are quantitatively consistent with I D Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and sub-threshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Svizhenko, Alexei↗
NASA NTRS2001

Quantum Mechanical Modeling of Ballistic MOSFETs

The objective of this project was to develop theory, approximations, and computer code to model quasi 1D structures such as nanotubes, DNA, and MOSFETs: (1) Nanotubes: Influence of defects on ballistic transport, electro-mechanical properties, and metal-nanotube coupling; (2) DNA: Model electron transfer (biochemistry) and transport experiments, and sequence dependence of conductance; and (3) MOSFETs: 2D doping profiles, polysilicon depletion, source to drain and gate tunneling, understand ballistic limit.

Svizhenko, Alexei↗
NASA NTRS1998

Simulation of Ultra-Small MOSFETs Using a 2-D Quantum-Corrected Drift-Diffusion Model

We describe an electronic transport model and an implementation approach that respond to the challenges of device modeling for gigascale integration. We use the density-gradient (DG) transport model, which adds tunneling and quantum smoothing of carrier density profiles to the drift-diffusion model. We present the current implementation of the DG model in PROPHET, a partial differential equation solver developed by Lucent Technologies. This implementation approach permits rapid development and enhancement of models, as well as run-time modifications and model switching. We show that even in typical bulk transport devices such as P-N diodes and BJTs, DG quantum effects can significantly modify the I-V characteristics. Quantum effects are shown to be even more significant in small, surface transport devices, such as sub-0.1 micron MOSFETs. In thin-oxide MOS capacitors, we find that quantum effects may reduce gate capacitance by 25% or more. The inclusion of quantum effects in simulations dramatically improves the match between C-V simulations and measurements. Significant quantum corrections also occur in the I-V characteristics of short-channel MOSFETs due to the gate capacitance correction.

Biegel, Bryan A.↗
NASA NTRS2009

Towards Accelerated Aging Methodologies and Health Management of Power MOSFETs (Technical Brief)

Understanding aging mechanisms of electronic components is of extreme importance in the aerospace domain where they are part of numerous critical subsystems including avionics. In particular, power MOSFETs are of special interest as they are involved in high voltage switching circuits such as drivers for electrical motors. With increased use of electronics in aircraft control, it becomes more important to understand the degradation of these components in aircraft specific environments. In this paper, we present an accelerated aging methodology for power MOSFETs that subject the devices to indirect thermal overstress during high voltage switching. During this accelerated aging process, two major modes of failure were observed - latch-up and die attach degradation. In this paper we present the details of our aging methodology along with details of experiments and analysis of the results.

Celaya, Jose R.↗
NASA NTRS2011

Prognostics of Power MOSFET

This paper demonstrates how to apply prognostics to power MOSFETs (metal oxide field effect transistor). The methodology uses thermal cycling to age devices and Gaussian process regression to perform prognostics. The approach is validated with experiments on 100V power MOSFETs. The failure mechanism for the stress conditions is determined to be die-attachment degradation. Change in ON-state resistance is used as a precursor of failure due to its dependence on junction temperature. The experimental data is augmented with a finite element analysis simulation that is based on a two-transistor model. The simulation assists in the interpretation of the degradation phenomena and SOA (safe operation area) change.

Celaya, Jose Ramon↗
NASA NTRS2011

Accelerated Aging with Electrical Overstress and Prognostics for Power MOSFETs

Power electronics play an increasingly important role in energy applications as part of their power converter circuits. Understanding the behavior of these devices, especially their failure modes as they age with nominal usage or sudden fault development is critical in ensuring efficiency. In this paper, a prognostics based health management of power MOSFETs undergoing accelerated aging through electrical overstress at the gate area is presented. Details of the accelerated aging methodology, modeling of the degradation process of the device and prognostics algorithm for prediction of the future state of health of the device are presented. Experiments with multiple devices demonstrate the performance of the model and the prognostics algorithm as well as the scope of application. Index Terms Power MOSFET, accelerated aging, prognostics

Saha, Sankalita↗
NASA NTRS2011

MOSFET Switching Circuit Protects Shape Memory Alloy Actuators

A small-footprint, full surface-mount-component printed circuit board employs MOSFET (metal-oxide-semiconductor field-effect transistor) power switches to switch high currents from any input power supply from 3 to 30 V. High-force shape memory alloy (SMA) actuators generally require high current (up to 9 A at 28 V) to actuate. SMA wires (the driving element of the actuators) can be quickly overheated if power is not removed at the end of stroke, which can damage the wires. The new analog driver prevents overheating of the SMA wires in an actuator by momentarily removing power when the end limit switch is closed, thereby allowing complex control schemes to be adopted without concern for overheating. Either an integral pushbutton or microprocessor-controlled gate or control line inputs switch current to the actuator until the end switch line goes from logic high to logic low state. Power is then momentarily removed (switched off by the MOSFET). The analog driver is suited to use with nearly any SMA actuator.

Gummin, Mark A.↗
NASA NTRS2011

Performance of a 100V Half-Bridge MOSFET Driver, Type MIC4103, Over a Wide Temperature Range

The operation of a high frequency, high voltage MOSFET (metal-oxide semiconductor field-effect transistors) driver was investigated over a wide temperature regime that extended beyond its specified range. The Micrel MIC4103 is a 100V, non-inverting, dual driver that is designed to independently drive both high-side and low-side N-channel MOSFETs. It features fast propagation delay times and can drive 1000 pF load with 10ns rise times and 6 ns fall times [1]. The device consumes very little power, has supply under-voltage protection, and is rated for a -40 C to +125 C junction temperature range. The floating high-side driver of the chip can sustain boost voltages up to 100 V. Table I shows some of the device manufacturer s specification.

Patterson, Richard L.↗
NASA NTRS2011

Probing the SEB Sensitive Depth of a Power MOSFET Using a Two-Photon Absorption Laser Method

This paper presents two-photon absorption test results on an engineering single-event burnout- (SEB-) sensitive power MOSFET to verify that the energy deposition/charge ionization in the highly-doped substrate does not contribute to SEB. It is shown that for a vertical power MOSFET, the SEB sensitive volume is the lightly doped epitaxial layer; the most sensitive region is under the polysllicon gate.

Lauenstein, Jean-Marie↗
NASA NTRS1997

Investigations into the Power MOSFET SEGR Phenomenon and its Physical Mechanism

The state of understanding of the destructive SEGR event in power MOSFETs is relatively mature with large published efforts, both experimental and theoretical. However, gasps remain in the uderstanding of the phenomenon, including unexplained anomalies, emperical-only dependencies on some important device and incident ion physical parameters, and limited insight into latent effets.

MOSFET SEGR↗
NASA NTRS2008

Current Leakage Evolution in Partially Gate Raptured Power MOSFETs

It has been observed that power MOSFETs can experience an SEGR and continue to function with altered parameters. We propose that there are three different types of SEGR modes; the micro-break, the thermal runaway, and the avalanche breakdown. Data that demonstrates these stages of device failure are presented as well as a proposed model for the micro-break. Brief discussions of the other modes, based on analysis combined with our interpretations of the older literature, are also given.

metal oxide semiconductor field-effect transistors↗
NASA NTRS2017

Radiation Hardness Study on SiC Power MOSFETs

As an emerging technology, silicon carbide (SiC) power MOSFETs are showing great potential for higher temperature/power rating, higher efficiency, and reduction in size and weight, which makes this technology ideal for high temperature, harsh environment applications such as downhole, medical, avionic, or even space applications. Radiation tolerance therefore becomes a critical aspect of the device performance in such environments. In this work, we explored radiation hardness of SiC devices to total ionizing dose (TID), neutron-induced single-event burnout (SEB), and heavy-ion induced single-event effects (SEE).

SiC↗
NASA NTRSDate not supplied

Design and Testing of a Hard-Fault Protection Circuit for a 1 kV SiC MOSFET Inverter

Due to increasingly high DC link voltages and further advancements in the current density of silicon carbide (SiC) MOSFETs, it has become evident that conventional IGBT protection methods are not sufficient to prevent exceeding the current rating of these devices during low-inductance fault events. This paper explores the use of an air core Rogowski coil topology to mitigate these hard fault events. The design of this circuit resulted in safe shutdown of a low impedance phase-to-phase fault in under one microsecond, tested up to DC link voltages of 1 kV. This paper details the theory, design, simulation, and successful test results of this method.

hard fault protection↗