Gas Emulation Demo (gased)
A simple physics gas network emulation and control logic design.
Rieger, Craig↗
SEARCH · Engineering Papers
Results for “LOGIC NETWORK”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Embedding global and collective in a torus network with message class map based tree path selection
Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
97 MATHEMATICS AND COMPUTING↗
Collective network for computer structures
A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
Blumrich, Matthias A.↗
Embedding global barrier and collective in a torus network
Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
97 MATHEMATICS AND COMPUTING↗
Automated Reconstruction of Control Logic for Programmable Logic Controller Forensics
This paper presents Similo, an automated scalable framework for control logic forensics in industrial control systems. Similo is designed to investigate denial of engineering operations (DEO) attacks, recently demonstrated to hide malicious control logic in a programmable logic controller (PLC) at field sites from an engineering software (at control center). The network traffic (if captured) contains substantial evidence to investigate DEO attacks including manipulation of control logic. Laddis, a state-of-the-art forensic approach for DEO attacks, is a binary-logic decompiler for the Allen-Bradley’s RSLogix engineering software and MicroLogix 1400 PLC. It is developed with extensive manual reverse engineering effort of the underlying proprietary network protocol and the binary control logic. Unfortunately, Laddis is not scalable and requires similar efforts to extend on other engineering software/PLCs. The proposed solution, Similo, is based on the observation that engineering software of different vendors are equipped with decompilers. Similo is a virtual-PLC framework that integrates the decompilers with their respective (previously-captured) ICS network traffic of control logic. It recovers the binary logic into a high-level source code (of the programming languages defined by IEC 61131-3 standard) automatically. Similo can work with both proprietary/open protocols without requiring protocol specifications and the binary formats of control logic. Thus, it is scalable to different ICS vendors. We evaluate Similo on three PLCs of two ICS vendors, i.e. MicroLogix 1400, MicroLogix 1100, and Modicon M221. These PLCs support proprietary protocols and the control logics written in two programming languages: Ladder Logic and Instruction List. The evaluation results show that Similo can accurately reconstruct a control logic from an ICS network traffic and can be used to investigate the DEO attacks effectively.
Ali qasim, Syed↗
LBNL Cell controller v1.0
Firmware and software of LBNL's Cell controller logic. Cell logic forms a high-speed data distribution network of FPGAs, transmitting data in a ring topology. This logic is used at ALS for the distribution of BPM data as part of the fast orbit feedback system.
Norum, William↗
Artificial Reasoning System for Symptom-Based Conditional Failure Probability Estimation Using Bayesian Network
Advances in nuclear power technologies require enhanced capabilities for operator advice and autonomous control. One of the first tasks in the development of such capabilities is the formulation of symptom-based conditional failure probabilities for structures, systems, and components (SSCs) of interest, for which the primary goal is to aid plant personnel in deducing the probabilistic performance status of the monitored SSCs and in detecting impending faults/failure. The task of conditional failure probability estimation is a bidirectional inference problem and shall be logically tackled by the Bayesian network (BN) approach. As a knowledge-based artificial intelligence tool and a probabilistic graphical model, BN offers the capability of reasoning under uncertainty and graphical representation emulating the physical behavior of the target SSC. This paper provides a systematic overview of the BN technique and the software tools for handling implementation of BN models, along with the associated knowledge representation and reasoning paradigm. Both operational data and expert judgement can be readily incorporated into the knowledge base of a BN model. The challenges with data availability are highlighted, and the general approach to target SSC identification is presented. Our focus is upon failure-prone and risk-important balance of plant assets, especially cases having strong operator involvement. An exemplary case study on the failure of a motor-driven centrifugal pump is also conducted to demonstrate the usefulness and technical feasibility of the proposed artificial reasoning system using an expert system shell.
Zhao, Xingang↗
Fault-tolerant optical interconnects for neutral-atom arrays
We analyze the use of photonic links to enable large-scale fault-tolerant connectivity of locally error-corrected modules based on neutral atom arrays. Our approach makes use of recent theoretical results showing the robustness of surface codes to boundary noise and combines recent experimental advances in atom-array quantum computing with logical qubits with optical quantum networking techniques. We find the conditions for fault tolerance can be achieved with local two-qubit Rydberg gate and nonlocal Bell-pair errors below 1% and 10%, respectively, without requiring distillation or space-time overheads. Realizing the interconnects with a lens, a single optical cavity, or an array of cavities enables—with sufficient multiplexing—a Bell-pair generation rate in the 1–50 MHz range. When directly interfacing logical qubits, this rate translates to error-correction cycles in the 25–2000 kHz range, satisfying all requirements for fault tolerance and in the upper range fast enough for 100 kHz logical clock cycles. Published by the American Physical Society 2025
Sinclair, Josiah (ORCID:0000000215238295)↗
Modular Spiking Neural Circuits for Mapping Long Short-Term Memory on a Neurosynaptic Processor
Due to the distributed and asynchronous nature of neural computation through low-energy spikes, brain-inspired hardware systems offer high energy efficiency and massive parallelism. One such platform is the IBM TrueNorth neurosynaptic system. Recently, TrueNorth compatible representation learning algorithms have emerged, achieving close to the state-of-the-art performance in various data sets. However, its application in temporal sequence processing models, such as recurrent neural networks (RNNs), is still only at the proof of concept level. There is an inherent difficulty in capturing temporal dynamics of an RNN using spiking neurons, which is only exasperated by the hardware constraints in connectivity and synaptic weight resolution. This paper presents a design flow that overcomes these difficulties and maps a special case of recurrent networks called long short-term memory (LSTM) onto a spike-based platform. The framework utilizes various approximation techniques, such as activation discretization, weight quantization, and scaling and rounding, spiking neural circuits that implement the complex gating mechanisms, and a store-and-release technique to enable neuron synchronization and faithful storage. While the presented techniques can be applied to map LSTM to any spiking neural network (SNN) simulator/emulator, here we choose the TrueNorth chip as the target platform by adhering to its hardware constraints. Three LSTM applications, parity check, extended Reber grammar, and question classification, are evaluated. The tradeoffs among accuracy, performance, and energy tradeoffs achieved on TrueNorth are demonstrated. Finally, this is compared with the performance on an SNN platform without hardware constraints, which represents the upper bound of the achievable accuracy.
97 MATHEMATICS AND COMPUTING↗
Knowledge represented using RDF semantic network in the concept of semantic web
The RDF(S) model has been declared as the basic model to capture knowledge of the semantic web. It provides a common and flexible way to decompose composed knowledge to elementary statements, which can be represented by RDF triples or by RDF graph vectors. From the logical point of view, elements of knowledge can be expressed using at most binary predicates, which can be converted to RDF-triples or graph vectors. However, it is not able to capture implicit knowledge representable by logical formulas. This contribution shows how existing approaches (semantic networks and clausal form logic) can be combined together with RDF to obtain RDF-compatible system with ability to represent implicit knowledge and inference over knowledge base.
97 MATHEMATICS AND COMPUTING↗
Integrated Approach to Density-Based Spatial Clustering of Applications with Noise and Dynamic Time Warping for Breakout Prediction in Slab Continuous Casting
Mold breakout is a catastrophic accident that has serious impacts on smooth production, slab quality, and caster equipment. Accurate identification and prediction of an impending breakout are always top priorities in continuous casting operations. In view of crucial common features of mold copper plate temperatures during a breakout, such as time lag and space inversion, the concepts of density-based spatial clustering of applications with noise and dynamic time warping are introduced, and an integrated novel method for breakout prediction is developed. Through extracting and fusing the representative singularity and approximation of temperature variation, the typical temporal and spatial temperature characteristics during breakout can be distinguished and predicted accurately. Compared with traditional methods of logical judgment and artificial neural network, the method based on clustering does not need to modify forecast thresholds or parameters artificially, which overcomes the limitation of model dependence on human beings, and demonstrates excellent adaptability and robustness for online abnormality prevention.
36 MATERIALS SCIENCE↗
FPGA/ASIC framework and method for requirements-based trust assessment
Described herein are various technologies for metrics-based assessment and trust verification of netlists for hardware logic devices (e.g., ASICs, FPGAs, etc.). A computing system translates a netlist of a hardware logic device into a Boolean network. The computing system generates and assigns metrics to edges of the Boolean network. The metrics comprise a coverage metric, a rare trigger metric, and an influence metric. Based upon the metrics, the computing system assigns the nodes in the Boolean network criticality values. The computing system determines a likelihood of a vulnerability in the netlist based upon the criticality values. The computing can output an indication as to whether the netlist is trusted based upon the determined likelihood of a vulnerability in the netlist.
97 MATHEMATICS AND COMPUTING↗
A Review of Software for Designing and Operating Quantum Networks
Quantum networks development is crucial to realizing a production-grade network that can support distributed sensing, secure communication, and utility-scale quantum computation. However, the transition from laboratory demonstration to deployable networks requires software implementations of architectures and protocols tailored to the unique constraints of quantum systems. This paper reviews the current state of software implementations for quantum networks, organized around a three-plane abstraction of infrastructure, logical, and control/service planes. We cover software for both designing quantum network protocols (e.g., SeQUeNCe, QuISP, and NetSquid) and operating testbeds, with a focus on essential control/service plane functions such as entanglement, topology, and resource management, in a proposed taxonomy. Our review highlights a persistent gap between theoretical architecture and protocol proposals and their realization in simulators or testbeds, particularly in dynamic topology and network management. We conclude by outlining open challenges and proposing a roadmap for developing scalable software architectures to enable hybrid, large-scale quantum networks.
Network Design↗
Fail-Safe Logic Design Strategies Within Modern FPGA Architectures
Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.
Bhakta, Priya A. [Univ. of New Mexico, Albuquerque↗
A Reconfigurable Neural Network ASIC for Detector Front-End Data Compression at the HL-LHC
Despite advances in the programmable logic capabilities of modern trigger systems, a significant bottleneck remains in the amount of data to be transported from the detector to off-detector logic where trigger decisions are made. We demonstrate that a neural network (NN) autoencoder model can be implemented in a radiation-tolerant application-specific integrated circuit (ASIC) to perform lossy data compression alleviating the data transmission problem while preserving critical information of the detector energy profile. For our application, we consider the high-granularity calorimeter from the Compact Muon Solenoid (CMS) experiment at the CERN Large Hadron Collider. The advantage of the machine learning approach is in the flexibility and configurability of the algorithm. By changing the NN weights, a unique data compression algorithm can be deployed for each sensor in different detector regions and changing detector or collider conditions. To meet area, performance, and power constraints, we perform quantization-aware training to create an optimized NN hardware implementation. The design is achieved through the use of high-level synthesis tools and the hls4ml framework and was processed through synthesis and physical layout flows based on a low-power (LP)-CMOS 65-nm technology node. The flow anticipates 200 Mrad of ionizing radiation to select gates and reports a total area of 3.6 mm 2 and consumes 95 mW of power. The simulated energy consumption per inference is 2.4 nJ. Furthermore, this is the first radiation-tolerant on-detector ASIC implementation of an NN that has been designed for particle physics applications.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Advancing Microelectronics Assurance while Preserving Confidentiality
Explore the source record for details and available documents.
Pattengale, Nicholas Dylan [Sandia National Labora↗
Utilizing Genetic Programming to Identify Failures in ICS Networks
Previously, researchers have attempted to apply machine learning techniques to network anomaly detection problems. Due to the staggering amount of variety that can occur in normal networks, the results have often been underwhelming. These challenges are far less pronounced when considering industrial control system (ICS) networks. The recurrent nature of these networks results in less noise and more consistent patterns for a machine learning algorithm to recognize. Here, we propose a method of evolving decision trees through genetic programming (GP) in order to detect network anomalies, such as device outages. Our approach extracts over a dozen features from network packet captures and netflows, normalizes them, and relates them in decision trees using fuzzy logic operators. Furthermore, the trees were used to detect three specific network events from three different points on the network across a statistically significant number of runs and achieved 100% accuracy on five of the nine experiments. When the trees attempted to detect more challenging events at points of presence further from the occurrence, the accuracy averaged to above 98%. Finally, using our method, all of the evolutionary cycles of the GP algorithm are computed a-priori, allowing the best resultant trees to be deployed as semi-real-time sensors with little overhead.
97 MATHEMATICS AND COMPUTING↗