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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

MacLeod, Todd C.↗
DOE OSTI2024

Direct pulse-level compilation of arbitrary quantum logic gates on superconducting qutrits

Advanced simulations and calculations on quantum computers require high-fidelity implementations of quantum operations. The universal gateset approach builds complex unitaries from a small set of primitive gates, often resulting in a long gate sequence, which is typically a leading factor in the total accumulated error. Compiling a complex unitary for processors with higher-dimensional logical elements, such as qutrits, exacerbates the accumulated error per unitary, since an even longer gate sequence is required. Optimal control methods promise time- and resource-efficient compact gate sequences and, therefore, higher fidelity. These methods generate pulses that can directly implement any complex unitary on a quantum device. In this work, we demonstrate that any arbitrary qubit and qutrit gate can be realized with high fidelity, which can significantly reduce the length of a gate sequence. We generate and test pulses for a large set of randomly selected arbitrary unitaries on several quantum processing units (QPUs): the Lawrence Livermore National Laboratory Quantum Device and Integration Testbed’s (QuDIT’s) standard QPU and three of Rigetti’s QPUs: Ankaa-2, Ankaa-9Q-1, and Aspen-M-3. On the QuDIT platform’s standard QPU, the average fidelity of random qutrit gates is 97.9 ± 0.5% measured with conventional QPT and 98.8 ± 0.6% from QPT with gate folding. Rigetti’s Ankaa-2 achieves random qubit gates with an average fidelity of 98.4 ± 0.5% (conventional QPT) and 99.7 ± 0.1% (QPT with gate folding). On Ankaa-9Q-1 and Aspen-M-3, the average fidelities with conventional qubit QPT measurements were higher than 99% (see Appendix). Here we show that optimal control gates are robust to drift for at least 3 h and that the same calibration parameters can be used for all implemented gates. Our work promises that the calibration overheads for optimal control gates can be made small enough to enable efficient quantum circuits based on this technique.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

Few-mode and anisotropic quantum transport in InSb nanoribbons using an all-van der Waals material-based gate

High-quality electrostatic gating is a fundamental ingredient for successful semiconducting device physics, and a key element of realizing clean quantum transport. Inspired by the widespread improvement of transport quality when two-dimensional van der Waals (vdW) materials are gated exclusively by other vdW materials, we have developed a method for gating non-vdW materials with an all-vdW gate stack, consisting of a hexagonal boron nitride dielectric layer and a few-layer graphite gate electrode. We demonstrate this gating approach on MOVPE-grown InSb nanoribbons (NRs), a novel variant of the InSb nanowire, with a flattened cross-section. In our all-vdW gated NR devices we observe conductance features that are reproducible and have low- to near-zero gate hysteresis. We also report quantized conductance, which persists to lower magnetic fields and longer channel lengths than typical InSb nanowire devices reported to date. Additionally, we observe level splitting that is highly anisotropic in an applied magnetic field, which we attribute to the ribbon cross-section. The performance of our devices is consistent with the reduced disorder expected from the all-vdW gating scheme, and marks the first report of ballistic, few-modes quantum transport in a non-vdW material with an all-vdW gate. Our results establish all-vdW gating as a promising approach for high-quality gating of non-vdW materials for quantum transport, which is in principle applicable generically, beyond InSb systems. In addition, the work showcases the specific potential of all-vdW gate/InSb NR devices for enabling clean quantum devices that may be relevant for spintronics and topological superconductivity studies.

InSb↗
DOE OSTI2026

Multitarget Rydberg gates via spatial blockade engineering

Multi-target gates offer the potential to reduce gate depth in syndrome extraction for quantum error correction. Although neutral-atom quantum computers have demonstrated native multi-qubit gates, existing approaches that avoid additional control or multiple atomic species have been limited to single-target gates. We propose single-control-multi-target CZ^n gates on a single-species neutral-atom platform that require no extra control and have gate durations comparable to standard CZ gates. Our approach leverages tailored interatomic distances to create an asymmetric blockade between the control and target atoms. Using a GPU-accelerated pulse synthesis protocol, we design smooth control pulses for CZZ and CZZZ gates, achieving fidelities of up to 99.55% and $99.24\%$, respectively, even in the presence of simulated atom placement errors and Rydberg-state decay. Our approach is most effective for N=2 (CZZ) and N=3 targets (CZZZ); for larger N, increasing spatial crowding of the targets introduces significant challenges for maintaining the required blockade asymmetry. This work presents a practical path to implementing low-overhead multi-target gates in single-species neutral-atom systems, significantly reducing the resource overhead for syndrome extraction. To motivate the impact of these gates, we apply a greedy scheduling algorithm and we demonstrate that our proposed gates can reduce the number of atom reconfiguration costs by up to 50% for color code syndrome extraction of code distances greater than 5.

Stein, Samuel A.↗
NASA NTRS1999

Computer Simulation Studies of Ion Channel Gating: Characteristics of the M2 Channel of Influenza-A Virus in a Phospholipid Bilayer

The 25 amino acids long, transmembrane fragment of the Influenza virus M2 protein forms a homotetrameric channel that transports protons across lipid bilayers. It has been postulated that high efficiency and selectivity of this process is due to gating by four histidine residues that occlude the channel lumen in the closed state. Two mechanisms of gating have been postulated. In one mechanism, the proton is "shuttled" through the gate by attaching to the delta nitrogen atom on the extracellular side of the imidazole ring, followed by the release of the proton attached to the epsilon nitrogen atom on the opposite side. In the second mechanism, the four histidines move away from each other due to electrostatic repulsion upon protonation, thus opening the gate sufficiently that a wire of water molecules can penetrate the gate. Then, protons are transported by "hopping" along the wire. In this paper, both mechanisms are evaluated in a series of molecular dynamics simulations by investigating stability of different protonation states of the channel that are involved in these mechanisms. For the shuttle mechanism, these are states with all epsilon protonated histidines, one biprotonated residue or one histidine protonated in the delta position. For the gate opening mechanism, this is the state in which all four histidines are biprotonated. In addition, a state with two biprotonated histidines is considered. For each system, composed of the protein channel embedded in phospholipid bilayer located between two water lamellae, a molecular dynamics trajectory of approximately 1.3 ns (after equilibration) was obtained. It is found that the states involved in the shuttle mechanism are stable during the simulations. Furthermore, the orientations and dynamics of water molecules near the gate are conducive to proton transfers involved in the shuttle. In contract, the fully biprotonated state, implicated in the gate opening mechanism, is not stable and the channel looses its structural integrity. If only two histidines are biprotonated the channel deforms but remains intact with the gate mostly closed. In summary, the results of this study lend support to the shuttle mechanism but not to the gate opening mechanism of proton gating in M2.

Schweighofer, Karl J.↗
DOE OSTI2020

Organic thin-film transistors with a bottom bilayer gate dielectric having a low operating voltage and high operational stability

This study reports on p-channel bottom-gate organic thin-film transistors (OTFT) that achieve low-voltage operation with a thin bilayer gate dielectric of CYTOP/HfO 2 that also leads to high operational stability. A bottom-gate geometry allows the thickness of the gate dielectric to be reduced to 17 nm, thereby increasing the gate dielectric capacitance density to a value of up to 258 nF/cm 2 . All OTFTs yielded threshold voltages (V TH ) lower than -1 V, thereby providing minimum operating voltage (gate to source voltage ~ V TH ) of -1 V with field-effect mobility values in the range from 0.3 to 0.8 cm 2 /Vs and subthreshold swing values below 100 mV/dec. Operational stability during DC bias stress was found similar to that measured in devices with a top-gate geometry, with about 1% of drain current change after 6 h. Here, using a double-stretched exponential function, the operational stability characteristics were modeled. It was found that by increasing the metal oxide layer thickness, the threshold voltage can shift toward positive values under DC stress tests. For CYTOP layer thicknesses above 15 nm, a thicker CYTOP layer was found to shift the threshold voltage in the opposite direction toward negative values. Furthermore, these p-channel bottom-gate organic transistor with a bilayer gate dielectric of CYTOP/HfO 2 combine high mobility, high operational stability, and lower voltage operation of -1 V compared to top-gate OTFTs.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Quantum computation of frequency-domain molecular response properties using a three-qubit iToffoli gate

The quantum computation of molecular response properties on near-term quantum hardware is a topic of substantial interest. Computing these properties directly in the frequency domain is desirable, but the circuits require large depth if the typical hardware gate set consisting of single- and two-qubit gates is used. While high-fidelity multipartite gates have been reported recently, their integration into quantum simulation and the demonstration of improved accuracy of the observable properties remains to be shown. Here, we report the application of a high-fidelity multipartite gate, the iToffoli gate, to the computation of frequency-domain response properties of diatomic molecules. The iToffoli gate enables a ~50% reduction in circuit depth and ~40% reduction in circuit execution time compared to the traditional gate set. We show that the molecular properties obtained with the iToffoli gate exhibit comparable or better agreement with theory than those obtained with the native CZ gates. Our work is among the first demonstrations of the practical usage of a native multi-qubit gate in quantum simulation, with diverse potential applications to near-term quantum computation.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Native Two-Qubit Gates in Fixed-Coupling, Fixed-Frequency Transmons Beyond Cross-Resonance Interaction

Fixed-frequency superconducting qubits demonstrate remarkable success as platforms for stable and scalable quantum computing. Cross-resonance gates have been the workhorse of fixed-coupling, fixed-frequency superconducting processors, leveraging the entanglement generated by driving one qubit resonantly with a neighbor’s frequency to achieve high-fidelity, universal controlled- () gates. Here, we use on-resonant and off-resonant microwave drives to go beyond cross-resonance, realizing natively interesting two-qubit gates that are not equivalent to gates. In particular, we implement and benchmark native i , , i SWAP , and b gates; in fact, any SU ( 4 ) unitary can be achieved using these techniques. Furthermore, we apply these techniques for an efficient construction of the B gate: a perfect entangler from which any two-qubit gate can be reached in only two applications. We show that these native two-qubit gates are better than their counterparts compiled from cross-resonance gates. We elucidate the resonance conditions required to drive each two-qubit gate and provide a novel frame tracking technique to implement them in Qiskit. Published by the American Physical Society 2024

Physics↗
DOE OSTI2023

Dancing the Quantum Waltz: Compiling Three-Qubit Gates on Four Level Architectures

Superconducting quantum devices are a leading technology for quantum computation, but they face several challenges. Gate errors, coherence errors and a lack of connectivity all contribute to low fidelity results. In particular, connectivity restrictions enforce a gate set that requires three-qubit gates to be decomposed into one- or two-qubit gates. This substantially increases the number of two-qubit gates that need to be executed. However, many quantum devices have access to higher energy levels. We can expand the qubit abstraction of |0〉 and |1〉 to a ququart which has access to the |2〉 and |3〉 state, but with shorter coherence times. This allows for two qubits to be encoded in one ququart, enabling increased virtual connectivity between physical units from two adjacent qubits to four fully connected qubits. This connectivity scheme allows us to more efficiently execute three-qubit gates natively between two physical devices.We present direct-to-pulse implementations of several three-qubit gates, synthesized via optimal control, for compilation of three-qubit gates onto a superconducting-based architecture with access to four-level devices with the first experimental demonstration of four-level ququart gates designed through optimal control. We demonstrate strategies that temporarily use higher level states to perform Toffoli gates and always use higher level states to improve fidelities for quantum circuits. We find that these methods improve expected fidelities with increases of 2x across circuit sizes using intermediate encoding, and increases of 3x for fully-encoded ququart compilation.

Litteken, Andrew↗
NASA NTRS1989

Monolithic transistor gate energy recovery system

Energy is recovered from an insulated gate semiconductor switch, such as a MOSFET, that is otherwise lost in the gate capacitance by producing a notch in the gate control voltage for an interval B following an interval A after initial application of a gate control voltage pulse for turning the switch on, and a notch for an interval C following termination of the gate control voltage pulse followed by interval D during which the switch is turned on again, where each interval is a period .DELTA.T given by ##EQU1## L.sub.s is the inductance (discrete and/or parasitic) in series with the gate electrode of the insulated gate semiconductor switch, and C.sub.in is the capacitance of that switch between its gate and source electrodes. The interval .DELTA.T may be provided directly by timing in a pulse forming circuit for the gate control voltage applied, or adaptively by sensing the gate voltage v.sub.g and comparing it with fixed progressively higher voltages v.sub.1, v.sub.2 and v.sub.3, where v.sub.2 is intermediate v.sub.1 and v.sub.3 which correspond to the lower and upper levels of v.sub.g as the switch is turned off and on.

Rippel, Wally E.↗
NASA NTRS2011

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Krasowski, Michael J.↗
DOE OSTI2024

Optimal Realization of Yang–Baxter Gate on Quantum Computers

Quantum computers provide a promising method to study the dynamics of many-body systems beyond classical simulation. On the other hand, the analytical methods developed and results obtained from the integrable systems provide deep insights on the many-body system. Quantum simulation of the integrable system not only provides a valid benchmark for quantum computers but is also the first step in studying integrable-breaking systems. The building block for the simulation of an integrable system is the Yang–Baxter gate. It is vital to know how to optimally realize the Yang–Baxter gates on quantum computers. Based on the geometric picture of the Yang–Baxter gates, the optimal realizations of two types of Yang–Baxter gates with a minimal number of controlled NOT (CNOT) or gates are presented. It is also shown how to systematically realize the Yang–Baxter gates via the pulse control. The different realizations on IBM quantum computers are tested and compared. It is found that the pulse realizations of the Yang–Baxter gates always have a higher gate fidelity compared to the optimal CNOT or realizations. On the basis of the above optimal realizations, the simulation of the Yang–Baxter equation on quantum computers is demonstrated. Finally, these results provide a guideline and standard for further experimental studies based on the Yang–Baxter gate.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

First-order crosstalk mitigation in parallel quantum gates driven with multi-photon transitions

Here, we demonstrate an order of magnitude reduction in the sensitivity to optical crosstalk for neighboring trapped-ion qubits during simultaneous single-qubit gates driven with individual addressing beams. Gates are implemented via two-photon Raman transitions, where crosstalk is mitigated by offsetting the drive frequencies for each qubit to avoid first-order crosstalk effects from inter-beam two-photon resonance. The technique is simple to implement, and we find that phase-dependent crosstalk due to optical interference is reduced on the most impacted neighbor from a maximal fractional rotation error of 0.185(4) without crosstalk mitigation to ≤0.006 with the mitigation strategy. Furthermore, we characterize first-order crosstalk in the two-qubit gate and avoid the resulting rotation errors for the arbitrary-axis Mølmer–Sørensen gate via a phase-agnostic composite gate. Finally, we demonstrate holistic system performance by constructing a composite CNOT gate using the improved single-qubit gates and phase-agnostic two-qubit gate. This work is done on the Quantum Scientific Computing Open User Testbed; however, our methods are widely applicable for individual addressing Raman gates and impose no significant overhead, enabling immediate improvement for quantum processors that incorporate this technique.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications

In this study, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2026

Trigonometric continuous-variable gates and hybrid quantum simulations of the sine-Gordon model

Hybrid qubit-qumode quantum computing platforms provide a natural setting for simulating interacting bosonic quantum field theories. However, existing continuous-variable gate constructions rely predominantly on polynomial functions of canonical quadratures. In this work, we introduce a complementary universality paradigm based on trigonometric continuous-variable gates, which enable a Fourier-like representation of bosonic operators and are particularly well suited for periodic and non-perturbative interactions. We present an ancilla-based framework for implementing trigonometric gates with arguments given by arbitrary Hermitian functions of qumode quadratures. The protocol yields unitary gates deterministically, and non-unitary gates through probabilistic post-selection. As a concrete application, we develop a hybrid qubit-qumode quantum simulation of the lattice sine-Gordon model. Using these gates, we prepare ground states via quantum imaginary-time evolution, simulate real-time dynamics, compute time-dependent vertex two-point correlation functions, and extract quantum kink profiles under topological boundary conditions. Our results demonstrate that trigonometric continuous-variable gates provide a physically natural framework for simulating interacting field theories on near-term hybrid quantum hardware, while establishing a parallel route to universality beyond polynomial gate constructions. We expect that the trigonometric gates introduced here to find broader applications, including quantum simulations of condensed matter systems, quantum chemistry, and biological models.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2022

Ultrathin ferroic HfO 2 –ZrO 2 superlattice gate stack for advanced transistors

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO 2 , which remains the material of choice to date. Here we report HfO 2 –ZrO 2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric–antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal–oxide–semiconductor capacitors is equivalent to an effective SiO 2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO 2 -based high-dielectric-constant gate stacks without scavenging the interfacial SiO 2 , which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO 2 –ZrO 2 multilayers, stabilized with competing ferroelectric–antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO 2 -based high-dielectric-constant materials.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Benchmarking and Fidelity Response Theory of High-Fidelity Rydberg Entangling Gates

The fidelity of entangling operations is a key figure of merit in quantum information processing, especially in the context of quantum error correction. High-fidelity entangling gates in neutral atoms have seen remarkable advancement recently. A full understanding of error sources and their respective contributions to gate infidelity will enable the prediction of fundamental limits on quantum gates in neutral atom platforms with realistic experimental constraints. In this work, we implement the time-optimal Rydberg controlled-Z (CZ) gate, design a circuit to benchmark its fidelity, and achieve a fidelity, averaged over symmetric input states, of 0.9971 ( 5 ) , downward corrected for leakage error, which together with our recent work [Nature 634, 321–327 (2024)] forms a new state of the art for neutral atoms. The remaining infidelity is explained by an error model, consistent with our experimental results over a range of gate speeds, with varying contributions from different error sources. Further, we develop a fidelity response theory to efficiently predict infidelity from laser noise with nontrivial power spectral densities and derive scaling laws of infidelity with gate speed. Besides its capability of predicting gate fidelity, we also utilize the fidelity response theory to compare and optimize gate protocols, to learn laser frequency noise, and to study the noise response for quantum simulation tasks. Finally, we predict that a CZ gate fidelity of ≳ 0.999 is feasible with realistic experimental upgrades. Published by the American Physical Society 2025

Tsai, Richard Bing-Shiun (ORCID:0000000286758677)↗
DOE OSTI2025

Controlled gate networks: theory and application to eigenvalue estimation

We introduce a new scheme for quantum circuit design called controlled gate networks. Rather than trying to reduce the complexity of individual unitary operations, the new strategy is to toggle between all of the unitary operations needed with the fewest number of gates. We present the general theory of controlled gate networks and show that, under quite general conditions, it can significantly reduce the number of two-qubit gates needed to produce linear combinations of unitary operators. The first example we consider is a variational subspace calculation for a two-qubit system. The second example is estimating the eigenvalues of a two-qubit Hamiltonian via the rodeo algorithm (Choi et al. in Phys Rev Lett 127(4):040505, 2021. https://doi.org/10.1103/PhysRevLett.127.040505) using operators that we call controlled reversal gates. We use the Quantinuum H1-2 and IBM Perth devices to realize the quantum circuits. The third example is the application of controlled gate networks to the controlled time evolution of a free nucleon on a three-dimensional lattice. For all of the examples, we show very substantial reductions in the number of two-qubit gates required. Our work demonstrates that controlled gate networks are a useful tool for reducing gate complexity in quantum algorithms for quantum many-body problems such as those relevant to nuclear physics.

Bee-Lindgren, Max [Georgia Institute of Technology↗