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Small lightweight multiplexer incorporates IG-FETs /Insulated Gate-Field Effect Transistors/ for all digital logic functions, including the internally generated 3.6-kHz clock. It consists of 30 primary channels, each of which is sampled 120 times per second.
Phenomenological study of radiation damage and recoverability of metal oxide field effect transistors
Two dimensional numerical analysis of current saturation mechanism for junction field effect transistors with small and large length-to-width ratio values
The ferroelectric channel in a Metal-Ferroelectric-Semiconductor Field Effect Transistor (MFSFET) can partially change its polarization when the gate voltage near the polarization threshold voltage. This causes the MFSFET Drain current to change with repeated pulses of the same gate voltage near the polarization threshold voltage. A previously developed model [11, based on the Fermi-Dirac function, assumed that for a given gate voltage and channel polarization, a sin-le Drain current value would be generated. A study has been done to characterize the effects of partial polarization on the Drain current of a MFSFET. These effects have been described mathematically and these equations have been incorporated into a more comprehensive mathematical model of the MFSFET. The model takes into account the hysteresis nature of the MFSFET and the time dependent decay as well as the effects of partial polarization. This model defines the Drain current based on calculating the degree of polarization from previous gate pulses, the present Gate voltage, and the amount of time since the last Gate volta-e pulse.
The threshold voltages of a carbon-nanotube (CNT) field-effect transistor (FET) are studied. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, and this makes the device characteristics quite unique. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and inversion and accumulation threshold voltages (V(sub Ti), and V(sub Ta)) are derived. V(sub Ti) of the CNTFETs has a much stronger doping dependence than that of the metal-oxide- semiconductor FETs, while V(sub Ta) of both devices depends weakly on doping with the same functional form.
An electronic simulation model has been developed of a ferroelectric field effect transistor (FFET). This model can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The model uses a previously developed algorithm that incorporates partial polarization as a basis for the design. The model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current has values matching actual FFET's, which were measured experimentally. The input and output resistance in the model is similar to that of the FFET. The model is valid for all frequencies below RF levels. A variety of different ferroelectric material characteristics can be modeled. The model can be used to design circuits using FFET'S with standard electrical simulation packages. The circuit can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The model is a drop in library that integrates seamlessly into a SPICE simulation. A comparison is made between the model and experimental data measured from an actual FFET.
Proton irradiation effects in MOS and junction field effect transistors and integrated circuits
The derivation of the circuitry of a field effect transistor (FET) model, the procedure for adapting the model to automated statistical analysis program (ASAP), and the results of applying ASAP on this model are described.
A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.
This paper discusses the electrical properties of the complementary heterojunction field-effect transistor (CHFET) at 4K, including the gate leakage current, the subthreshold transconductance, and the input-referred noise voltage.
Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.
Insulated gate field effect transistors using cadmium selenide or telluride as piezoelectric semiconductor material
The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.
The internal physical mechanism that governs the current conduction in junction-gate field effect transistors is studied. A numerical method of analyzing the devices with different length-to-width ratios and doping profiles is developed. This method takes into account the two dimensional character of the electric field and the field dependent mobility. Application of the method to various device models shows that the channel width and the carrier concentration in the conductive channel decrease with increasing drain-to-source voltage for conventional devices. It also shows larger differential drain conductances for shorter devices when the drift velocity is not saturated. The interaction of the source and the drain gives the carrier accumulation in the channel which leads to the space-charge-limited current flow. The important parameters for the space-charge-limited current flow are found to be the L/L sub DE ratio and the crossover voltage.
Metal-oxide semiconductor field-effect transistor /MOSFET/ analog-gate circuit adapts well to integrated circuits. It provides better system isolation than a transformer, while size and weight are appreciably reduced.
Film deposition of cermet resistors on same chip with metal nitride oxide silicon field effect transistors permits protection of contamination sensitive active devices from contaminants produced in cermet deposition and definition processes. Additional advantages include lower cost, greater reliability, and space savings.
There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.
Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K are presented. It is shown that the CHFET exhibits normal transistor operation down to 6 K. Some of the details of the transistor operation, such as the gate-voltage dependence of the channel potential, are analyzed. The gate current is examined and is shown to be due to several mechanisms acting in parallel. These include field-emission and thermionic-field-emission, conduction through a temperature-activated resistance, and thermionic emission. The input referred noise for n-channel CHFETs is presented and discussed. The noise has the spectral dependence of 1/f noise, but does not exhibit the usual area dependence.