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A method is described for determining the realizability of a sequential machine with trigger or set-reset flip-flop memory elements when the feedback of the machine is given by a Boolean function. Feedbacks in several types of sequential machines with different memory elements are compared, showing the memory specifications allowing the realization of such machines.
For binary digit array of N bits, use N noise sources to feed N nonlinear operators; each flip-flop in digit array is set by nonlinear operator to reflect whether amplitude of generator which feeds it is above or below mean value of generated noise. Fixed-point uniform distribution random number generation method can also be used to generate random numbers with other than uniform distribution.
Phase-lock loop references all its operations to fixed high-frequency service clock operating at highest speed which digital circuits permit. Wide-range control circuit provides linear control of frequency of reference signal. It requires only two counters in combination with control circuit consisting only of flip-flop and gate.
Variable load has very fast response under wide range of simulated dynamic operating conditions, and can accept inputs up to 1000 watts. Many types of signals may be applied to load. Variable pulse generator and flip-flop produce rectangular waveform. Other signals include steady state step and single pulse.
A number of fundamentally ultra-reliable, all-magnetic logic circuits are developed using as a basis a single element ferrite structure wired as a logic delay element. By making minor additions or changes to the basic wiring pattern of the delay element other logic functions such as OR, AND, NEGATION, MAJORITY, EXCLUSIVE-OR, and FAN-OUT are developed. These logic functions are then used in the design of a full-adder, a set/reset flip-flop, and an edge detector. As a demonstration of the utility of all the developed devices, an 8-bit, all-magnetic, logic arithmetic unit capable of controlled addition, subtraction, and multiplication is designed. A new basic ferrite logic element and associated complementary logic scheme with the potential of improved performance is also described. Finally, an improved batch process for fabricating joint-free power drive and logic interconnect conductors for this basic class of all-magnetic logic is presented.
A system is described for locating lightning strikes by developing the coordinates of a pair of lines, each of which is produced at a reference sensing station. At each station there are a pair of directional antennas which produce analog signals responsive to a lightning stroke. These analog signals are fed to a pair of integrators which integrate the signals for a predetermined period of time so as to produce the X and Y coordinate of a particular line. The analog signals are also fed through a square rooter, a Schmitt trigger circuit, and flip-flops to produce pulses for starting and stopping the integrators. The system at the remote station is similar to that at the central station and is tied to the circuitry at the central station through logic circuits to minimize the chance of error from spurious signals. Computers, printers, and plotters are utilized to plot the exact location of the lightning stroke.
Frequency-independent circuits measure amplitude of sine waves via Schmitt-trigger circuits, pair of inverters, and two flip-flop stages. Accuracy of unit is limited by Schmitt trigger threshold levels, which depend on temperature and on component variations from unit to unit.
Circuit arrangements for flip-flops, counters, and clock drivers in redundant systems ensure that control is synchronously transferred to surviving components when failure occurs. In addition to original application to spacecraft systems, redundant circuits have terrestrial uses in power generators, solar-energy converters, computers, vehicle controllers, and other systems demanding high reliability.
Algorithms are presented for differentiation and integration of Boolean functions by means of Karnaugh maps. The algorithms are considered simple when the number of variables is six or less; in this case Boolean differentiation and integration is said to be as easy as the Karnaugh map method of simplifying switching functions. It is suggested that the algorithms would be useful in the analysis of faults in combinational systems and in the synthesis of asynchronous sequential systems which utilize edge-sensitive flip-flops.
Formal procedures for synthesis of asynchronous sequential system using commercially available edge-sensitive flip-flops are developed. Boolean differential is defined. The exact number of compatible integrals of a Boolean differential were calculated.
Simple circuit divides frequency by preselected odd number. Exclusive-OR gate, divide-by-N circuit, and flip-flop are only components. Input pulses must be symmetrical.
Previous analytical models were extended to predict cosmic ray-induced soft error rates in static MOS memory devices. The effect is due to ionization and can be introduced by high energy, heavy ion components of the galactic environment. The results indicate that the sensitivity of memory cells is directly related to the density of the particular MOS technology which determines the node capacitance values. Hence, CMOS is less sensitive than e.g., PMOS. In addition, static MOS memory cells are less sensitive than dynamic ones due to differences in the mechanisms of storing bits. The flip-flop of a static cell is inherently stable against cosmic ray-induced bit flips. Predicted error rates on a CMOS RAM and a PMOS shift register are in general agreement with previous spacecraft flight data.
New gated oscillator generates bursts of high-frequency sine waves, square waves, and triangular waves in response to control signals. Each burst starts at zero phase, with tight tolerances on signal amplitude and frequency. Frequencies in megahertz range are made possible by using high-speed comparators and high-speed flip-flop as fast-response threshold detector.
The entire complement of standard cells and components, except for the set-reset flip-flop, was completed. Two levels of checking were performed on each device. Logic cells and topological layout are described. All the related computer programs were coded and one level of debugging was completed. The logic for the test chip was modified and updated. This test chip served as the first test vehicle to exercise the standard cell complementary MOS(C-MOS) automatic artwork generation capability.
It is shown that the use of redundant on-chip circuitry improves the testability of an entire VLSI circuit. In the study described here, five techniques applied to a two-bit ripple carry adder are compared. The techniques considered are self-oscillation, self-comparison, partition, scan path, and built-in logic block observer. It is noted that both classical stuck-at faults and nonclassical faults, such as bridging faults (shorts), stuck-on x faults where x may be 0, 1, or vary between the two, and parasitic flip-flop faults occur in IC structures. To simplify the analysis of the testing techniques, however, a stuck-at fault model is assumed.
Data taken from tests involving heavy ions in the Berkeley 88 in. cyclotron being directed at low power Schottky barrier devices are reported. The tests also included trials in the Harvard cyclotron with 130 MeV protons, and at the U.C. Davis cyclotron using 56 MeV protons. The experiments were performed to study the single event upsets in MSI logic devices containing flip-flops. Results are presented of single-event upsets (SEU) causing functional degradation observed in post-exposure tests of six different devices. The effectiveness of the particles in producing SEUs in logic device functioning was found to be directly proportional to the proton energy. Shielding was determined to offer negligible protection from the particle bombardment. The results are considered significant for the design and fabrication of LS devices for space applications.
Numerical optical computing is discussed. A design for an optical pulse generator using a Hughes Liquid crystal light valve and intended for application as an optical clock in a numerical optical computer is considered. The pulse generator is similar in concept to the familiar electronic multivibrator, having a flip-flop and delay units.
Neural architecture search (NAS) is a powerful approach for automating model design, but existing methods often optimize for accuracy alone or rely on proxy metrics such as bit operations (BOPs) that correlate poorly with hardware cost. This gap is particularly large for FPGA deployment, where cost is dominated by a multi-dimensional budget of lookup tables, DSPs, flip-flops, BRAM, and latency. We present the Surrogate Neural Architecture Codesign Package (SNAC-Pack), an open-source AutoML framework for hardware-aware neural architecture codesign and end-to-end FPGA deployment. SNAC-Pack runs a multi-objective global search with Optuna and NSGA-II, loading trials to a shared SQLite store that enables parallel workers across compute nodes. A hardware surrogate model outputs per-trial resource and latency estimates, avoiding the synthesis cost that would otherwise dominate the search loop. A local search stage then applies quantization-aware training (QAT) together with iterative magnitude pruning in a combined compression loop, after which the final model is synthesized to FPGA firmware via the hls4ml Python library. A YAML configuration and an optional agentic frontend let users run the pipeline on new datasets without modifying the framework. We demonstrate SNAC-Pack on jet classification at the Large Hadron Collider and superconducting qubit readout, discovering compact architectures that match or exceed strong baselines on the task metric while reducing FPGA resource utilization and, in the qubit readout case, reducing the design space exploration process from months of manual fine-tuning to hours of automated search.