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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Initial research on switched and modulated networks, tunable and bandwith-adjustable filter and FET current density for device circuit interaction in power processing
GaN/InGaN microLEDs are a very promising technology for next-generation displays. Switching control transistors and their integration are key components in achieving high-performance, efficient displays. Monolithic integration of microLEDs with GaN switching devices provides an opportunity to control microLED output power with capacitive (voltage)-controlled rather than current-controlled schemes. This approach can greatly reduce system complexity for the driver circuit arrays while maintaining device opto-electronic performance. In this work, we demonstrate a 3-terminal GaN micro-light emitting transistor that combines a GaN/InGaN blue tunneling-based microLED with a GaN n-channel FET. Further, the integrated device exhibits excellent gate control, drain current control, and optical emission control. This work provides a promising pathway for future monolithic integration of GaN FETs with microLED to enable fast switching, high-efficiency microLED display and communication systems.
An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.
A steep-slope (SS) field effect transistor (FET) including a FET having a source region and a drain region, and a threshold switching device in direct contact with the source region or the drain region of the FET. Fabricating the steep-slope (SS) field effect transistor (FET) includes fabricating an AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) having a source region and a drain region, depositing a first electrode layer directly on the source region or the drain region, depositing a threshold switching layer directly on the first electrode layer, and depositing a second electrode layer directly on the threshold switching layer.
An introduction to overall IR array concepts and particular array designs is presented, and examples of laboratory and observational data obtained with IR arrays are given. Hybrid array designs, extrinsic silicon accumulation-mode charge injection devices, and switched-FET or switched-sample photoconductor techniques are summarized. Three recent astronomical observation projects which used IR arrays are examined.
This paper describes the fabrication and application of GaAs FET's, both as discrete microwave devices and as the key active components in monolithic microwave integrated circuits. The performance of these devices and circuits is discussed for frequencies ranging from 3 to 25 GHz. The crucial fabrication step is the formation of the submicron gate by electron-beam lithography.
Pulse Width Modulator (PWM) Controllers are the heart of switching power supply systems in development today. The PWMs considered here have the same integration advantages as many other controllers but it also includes the interface drivers for the follow-on power Field Effect Transistors (FET). Previous work on these types of devices looked into the required test methodologies [ 11 and the impact of radiation on the soft start and shutdown circuits of typically incorporated in the technology [2]. Taking advantage of this previous work this study was undertaken to determine the single event destructive and transient susceptibility of the Linfinity SG1525A Pulse Width Modulator Controller. The device was monitored for transient interruptions in the output signals and for destructive events induced by exposing it to a heavy ion beam at the Texas A&M University Cyclotron Single Event Effects Test Facility. After exposing these devices to the beam, a new upset mode has been identified that can lead to catastrophic power supply system failure if this event would occur while drive power FETs off the two device outputs. The devices and the test methods used will be described first. This will be followed by a brief description of the data collected to date (not all data can be presented with the length constraints of the summary) and a summary of the key results.
Abstract Nanoporous graphene (NPG) can exhibit a uniform electronic band gap and rationally‐engineered emergent electronic properties, promising for electronic devices such as field‐effect transistors (FETs), when synthesized with atomic precision. Bottom‐up, on‐surface synthetic approaches developed for graphene nanoribbons (GNRs) now provide the necessary atomic precision in NPG formation to access these desirable properties. However, the potential of bottom‐up synthesized NPG for electronic devices has remained largely unexplored to date. Here, FETs based on bottom‐up synthesized chevron‐type NPG (C‐NPG), consisting of ordered arrays of nanopores defined by laterally connected chevron GNRs, are demonstrated. C‐NPG FETs show excellent switching performance with on–off ratios exceeding 10 4 , which are tightly linked to the structural quality of C‐NPG. The devices operate as p‐type transistors in the air, while n‐type transport is observed when measured under vacuum, which is associated with reversible adsorption of gases or moisture. Theoretical analysis of charge transport in C‐NPG is also performed through electronic structure and transport calculations, which reveal strong conductance anisotropy effects in C‐NPG. The present study provides important insights into the design of high‐performance graphene‐based electronic devices where ballistic conductance and conduction anisotropy are achieved, which could be used in logic applications, and ultra‐sensitive sensors for chemical or biological detection.
Device can be obtained by driving basic circuit through nonlinear FET input stage. Frequency of VCO is linearized with FET and total variance is varactor controlled. Experimental device exhibited linearity of better than plus or minus one percent for total frequency of plus or minus 10 millihertz.
Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.
Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as a class of materials with exceptional electronic, optical, and mechanical properties, making them highly tunable for diverse applications in nanoelectronics, optoelectronics, and catalysis. Here, this review focuses on substitutional doping of TMDs, a key strategy to tailor their properties and enhance device performance, with a focus on its applications over the past five years (2019–2024). We delve into both theoretical and experimental doping approaches, including established methods like chemical vapor transport (CVT) and chemical vapor deposition (CVD) alongside liquid phase exfoliation (LPE) and post-synthesis treatments. Advanced growth techniques are also explored. Challenges like dopant uniformity, concentration control, and stability are addressed. The influence of various dopants on the electronic band structure, carrier concentration, and defect engineering is analyzed in detail. We further explore recent advancements in utilizing doped TMDs for field-effect transistors (FETs), photodetectors, sensors, photovoltaics, optoelectronic devices, energy storage and conversion, and even quantum computers. By examining both the potential and limitations of substitutional doping, this review aims to propel future research and technological advancements in this exciting field.
Despite successful applications of solution-processed organic–inorganic hybrid perovskites (OIHPs) such as archetypical methylammonium lead iodide (MAPI) in high-performance optoelectronic devices including solar cells and light emitting diodes, their application in field-effect transistors (FETs) remains relatively limited due to the unresolved issues caused by ion migration in OIHPs, such as screening of gate electric fields, lowered device on-off ratios and field-effect mobility, and large hysteresis in the FET transfer characteristics. Here, we report improved performances of the MAPI-based FET via a polymer-additive-based grain boundary (GB) passivation approach that suppresses the ion migration. Polycaprolactone (PCL) was incorporated into the MAPI FET as a GB-passivation additive as confirmed by scanning electron and atomic force microscopies. Unlike the typical n-type behavior and large transfer hysteresis in the starting, pristine MAPI FETs, the GB passivation by PCL led to a drastically reduced hysteresis in FET transfer characteristics, while hinting at an ambipolar transport and slight improvement in mobility, indicating a reduced ion migration in the PCL-incorporated MAPI FET. The effect of PCL GB passivation in suppressing ion migration was directly confirmed by the measured, increased activation energy for ion migration in the PCL-incorporated MAPI. Here, the results not only represent the first report of the polymer-additive-based mitigation of the ion migration in the MAPI FET but also suggest potential utilities of the approach for enabling high-performance OIHP FETs and electronic devices in general.
Despite intensive research of nanomaterials-based field-effect transistors (FETs) as a rapid diagnostic tool, it remains to be seen for FET sensors to be used for clinical applications due to a lack of stability, reliability, reproducibility, and scalability for mass production. In this work, we propose a remote floating-gate (RFG) FET configuration to eliminate device-to-device variations of two-dimensional reduced graphene oxide (rGO) sensing surfaces and most of the instability at the solution interface. Also, critical mechanistic factors behind the electrochemical instability of rGO such as severe drift and hysteresis were identified through extensive studies on rGO–solution interfaces varied by rGO thickness, coverage, and reduction temperature. rGO surfaces in our RFGFET structure displayed a Nernstian response of 54 mV/pH (from pH 2 to 11) with a 90% yield (9 samples out of total 10), coefficient of variation (CV) < 3%, and a low drift rate of 2%, all of which were calculated from the absolute measurement values. As proof-of-concept, we demonstrated highly reliable, reproducible, and label-free detection of spike proteins of severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) in a saliva-relevant media with concentrations ranging from 500 fg/mL to 5 μg/mL, with an R 2 value of 0.984 and CV < 3%, and a guaranteed limit of detection at a few pg/mL. Taken together, this new platform may have an immense effect on positioning FET bioelectronics in a clinical setting for detecting SARS-CoV-2.
Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET
A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.
The rational bottom-up synthesis of graphene nanoribbons (GNRs) provides atomically precise control of widths and edges that give rise to a wide range of electronic properties promising for electronic devices such as field-effect transistors (FETs). Since the bottom-up synthesis commonly takes place on catalytic metallic surfaces, the integration of GNRs into such devices requires their transfer onto insulating substrates, which remains one of the bottlenecks in the development of GNR-based electronics. Herein, we report on a method for the transfer-free placement of GNRs on insulators. This involves growing GNRs on a gold film deposited onto an insulating layer followed by gentle wet etching of the gold, which leaves the nanoribbons to settle in place on the underlying insulating substrate. Scanning tunneling microscopy and Raman spectroscopy confirm that atomically precise GNRs of high density uniformly grow on the gold films deposited onto SiO 2 /Si substrates and remain structurally intact after the etching process. We have also demonstrated transfer-free fabrication of ultrashort channel GNR FETs using this process. A very important aspect of the present work is that the method can scale up well to 12 in. wafers, which is extremely difficult for previous techniques. Our work here thus represents an important step toward large-scale integration of GNRs into electronic devices.
Abstract Despite significant progress in solution‐processing of 2D materials, it remains challenging to reliably print high‐performance semiconducting channels that can be efficiently modulated in a field‐effect transistor (FET). Herein, electrochemically exfoliated MoS 2 nanosheets are inkjet‐printed into ultrathin semiconducting channels, resulting in high on/off current ratios up to 10 3 . The reported printing strategy is reliable and general for thin film channel fabrication even in the presence of the ubiquitous coffee‐ring effect. Statistical modeling analysis on the printed pattern profiles suggests that a spaced parallel printing approach can overcome the coffee‐ring effect during inkjet printing, resulting in uniform 2D flake percolation networks. The uniformity of the printed features allows the MoS 2 channel to be hundreds of micrometers long, which easily accommodates the typical inkjet printing resolution of tens of micrometers, thereby enabling fully printed FETs. As a proof of concept, FET water sensors are demonstrated using printed MoS 2 as the FET channel, and printed graphene as the electrodes and the sensing area. After functionalization of the sensing area, the printed water sensor shows a selective response to Pb 2+ in water down to 2 ppb. This work paves the way for additive nanomanufacturing of FET‐based sensors and related devices using 2D nanomaterials.
In this article, we performed a comprehensive combined experimental and modeling study on the polarization reset mechanisms of floating body (i.e., channel) ferroelectric FETs, an important class of device with growing interests due to added functionalities and improved reliabilities. Using fully-depleted silicon-on-insulator (FDSOI) FeFET as a classical example, we demonstrate that: 1) without hole generation mechanisms, floating body FeFETs during reset is simply a capacitor divider, with negligible ferroelectric voltage drop for switching; ii) Band-to-band-tunneling (BTBT) around gate-to-S/D overlap even with zero drain bias generates holes to facilitate the reset in FDSOI FeFET, though at a slower speed and hold the reset state; iii) With scaling, S/D inner fringe field can enable fast reset, thus offering a potential efficiency boost approach; iv) a compact FDSOI FeFET model is developed that can capture the BTBT effect and reproduce the observed behaviors; v) the reset mechanism is also validated in a NAND string composed of FDSOI FeFETs, demonstrating its relevant applications. These insights show the strategies in improving reset efficiency, i.e., enhanced BTBT and inner fringe field.