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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1985

Performance study of a data flow architecture

Teams of scientists studied data flow concepts, static data flow machine architecture, and the VAL language. Each team mapped its application onto the machine and coded it in VAL. The principal findings of the study were: (1) Five of the seven applications used the full power of the target machine. The galactic simulation and multigrid fluid flow teams found that a significantly smaller version of the machine (16 processing elements) would suffice. (2) A number of machine design parameters including processing element (PE) function unit numbers, array memory size and bandwidth, and routing network capability were found to be crucial for optimal machine performance. (3) The study participants readily acquired VAL programming skills. (4) Participants learned that application-based performance evaluation is a sound method of evaluating new computer architectures, even those that are not fully specified. During the course of the study, participants developed models for using computers to solve numerical problems and for evaluating new architectures. These models form the bases for future evaluation studies.

Adams, George↗
NASA NTRSDate not supplied

DIP Architecture and Data Integration Services

This workshop will cover DIP architecture and data integration services. Participants will get a look at how the DIP architecture is set-up as well as how data integration services are planned to be hosted on the platform. The DIP architecture review is intended to cover how DIP was envisioned and how DIP is being developed to address data needs across the industry. Participants will have a chance to provide feedback on the DIP architecture and gain insight into how one might interface with the DIP to send or receive data. The data integration services portion is intended to cover DIP’s technical approach to data integration. As an example implementation, there will be a first look at possible data fusion on the platform, including utilizing NASA’s Fuser, and tailoring for industry data consumers. Descriptions, at a high-level, of input to and output of the Fuser will also be discussed.

ATM-X↗
NASA NTRSDate not supplied

Recap of DIP Workshop Series: #1 DIP Architecture and Data Integrations Services

This workshop will cover DIP architecture and data integration services to obtain feedback from America for Airlines (A4A) Air Traffic Management Council (ATMC). Participants will get a look at how the DIP architecture is set-up as well as how data integration services are planned to be hosted on the platform. The DIP architecture review is intended to cover how DIP was envisioned and how DIP is being developed to address data needs across the industry. Participants will have a chance to provide feedback on the DIP architecture and gain insight into how one might interface with the DIP to send or receive data. The data integration services portion is intended to cover DIP’s technical approach to data integration. As an example implementation, there will be a first look at possible data fusion on the platform, including utilizing NASA’s Fuser, and tailoring for industry data consumers. Descriptions, at a high-level, of input to and output of the Fuser will also be discussed.

ATM-X↗
NASA NTRS2006

The NASA Space Communications Data Networking Architecture

The NASA Space Communications Architecture Working Group (SCAWG) has recently been developing an integrated agency-wide space communications architecture in order to provide the necessary communication and navigation capabilities to support NASA's new Exploration and Science Programs. A critical element of the space communications architecture is the end-to-end Data Networking Architecture, which must provide a wide range of services required for missions ranging from planetary rovers to human spaceflight, and from sub-orbital space to deep space. Requirements for a higher degree of user autonomy and interoperability between a variety of elements must be accommodated within an architecture that necessarily features minimum operational complexity. The architecture must also be scalable and evolvable to meet mission needs for the next 25 years. This paper will describe the recommended NASA Data Networking Architecture, present some of the rationale for the recommendations, and will illustrate an application of the architecture to example NASA missions.

Israel, David J.↗
NASA NTRS1988

Strategies for concurrent processing of complex algorithms in data driven architectures

The purpose is to document research to develop strategies for concurrent processing of complex algorithms in data driven architectures. The problem domain consists of decision-free algorithms having large-grained, computationally complex primitive operations. Such are often found in signal processing and control applications. The anticipated multiprocessor environment is a data flow architecture containing between two and twenty computing elements. Each computing element is a processor having local program memory, and which communicates with a common global data memory. A new graph theoretic model called ATAMM which establishes rules for relating a decomposed algorithm to its execution in a data flow architecture is presented. The ATAMM model is used to determine strategies to achieve optimum time performance and to develop a system diagnostic software tool. In addition, preliminary work on a new multiprocessor operating system based on the ATAMM specifications is described.

Stoughton, John W.↗
NASA NTRS1991

Study Of Candidate Architectures For Data Processor

Report discusses candidate architectures for digital computer system, part of communication system in spacecraft. Primary issues in analysis; performance, rates of bit errors attributable to single-event upsets (caused by ionizing radiation), reliability, size, and dissipation of power.

Mcroberts, Lou↗
NASA NTRS1992

Processor architecture and data buffering

A set of architectures from three major architecture families: stack, register, and memory-to-memory is discussed. It is shown that scalable architectures are not applicable for low-density technologies because they require at least 32 words of local memory. Software support is shown to be capable of bridging the performance gap between scalable and nonscalable architectures. A register architecture with 32 words of local memory allocated interprocedurally outperforms scalable architectures with equal sizes local memories and even some with larger size local memories. The performance advantage of unscalable architectures becomes significant when in addition to quality compile-time support, a small cache is added to an unscalable architecture. A 32-register architecture with 512 byte cache executes 20 percent less cycles when compared with an 8-set multiple overlapping set organization.

Mulder, Hans↗
NASA NTRS1990

Strategies for concurrent processing of complex algorithms in data driven architectures

The performance modeling and enhancement for periodic execution of large-grain, decision-free algorithms in data flow architectures is examined. Applications include real-time implementation of control and signal processing algorithms where performance is required to be highly predictable. The mapping of algorithms onto the specified class of data flow architectures is realized by a marked graph model called ATAMM (Algorithm To Architecture Mapping Model). Performance measures and bounds are established. Algorithm transformation techniques are identified for performance enhancement and reduction of resource (computing element) requirements. A systematic design procedure is described for generating operating conditions for predictable performance both with and without resource constraints. An ATAMM simulator is used to test and validate the performance prediction by the design procedure. Experiments on a three resource testbed provide verification of the ATAMM model and the design procedure.

Stoughton, John W.↗
NASA NTRS1990

Strategies for concurrent processing of complex algorithms in data driven architectures

Performance modeling and performance enhancement for periodic execution of large-grain, decision-free algorithms in data flow architectures are discussed. Applications include real-time implementation of control and signal processing algorithms where performance is required to be highly predictable. The mapping of algorithms onto the specified class of data flow architectures is realized by a marked graph model called algorithm to architecture mapping model (ATAMM). Performance measures and bounds are established. Algorithm transformation techniques are identified for performance enhancement and reduction of resource (computing element) requirements. A systematic design procedure is described for generating operating conditions for predictable performance both with and without resource constraints. An ATAMM simulator is used to test and validate the performance prediction by the design procedure. Experiments on a three resource testbed provide verification of the ATAMM model and the design procedure.

Som, Sukhamoy↗
NASA NTRS1991

Mark 4A antenna control system data handling architecture study

A high-level review was conducted to provide an analysis of the existing architecture used to handle data and implement control algorithms for NASA's Deep Space Network (DSN) antennas and to make system-level recommendations for improving this architecture so that the DSN antennas can support the ever-tightening requirements of the next decade and beyond. It was found that the existing system is seriously overloaded, with processor utilization approaching 100 percent. A number of factors contribute to this overloading, including dated hardware, inefficient software, and a message-passing strategy that depends on serial connections between machines. At the same time, the system has shortcomings and idiosyncrasies that require extensive human intervention. A custom operating system kernel and an obscure programming language exacerbate the problems and should be modernized. A new architecture is presented that addresses these and other issues. Key features of the new architecture include a simplified message passing hierarchy that utilizes a high-speed local area network, redesign of particular processing function algorithms, consolidation of functions, and implementation of the architecture in modern hardware and software using mainstream computer languages and operating systems. The system would also allow incremental hardware improvements as better and faster hardware for such systems becomes available, and costs could potentially be low enough that redundancy would be provided economically. Such a system could support DSN requirements for the foreseeable future, though thorough consideration must be given to hard computational requirements, porting existing software functionality to the new system, and issues of fault tolerance and recovery.

Briggs, H. C.↗
NASA NTRS1987

Strategies for concurrent processing of complex algorithms in data driven architectures

The results of ongoing research directed at developing a graph theoretical model for describing data and control flow associated with the execution of large grained algorithms in a spatial distributed computer environment is presented. This model is identified by the acronym ATAMM (Algorithm/Architecture Mapping Model). The purpose of such a model is to provide a basis for establishing rules for relating an algorithm to its execution in a multiprocessor environment. Specifications derived from the model lead directly to the description of a data flow architecture which is a consequence of the inherent behavior of the data and control flow described by the model. The purpose of the ATAMM based architecture is to optimize computational concurrency in the multiprocessor environment and to provide an analytical basis for performance evaluation. The ATAMM model and architecture specifications are demonstrated on a prototype system for concept validation.

Stoughton, John W.↗
NASA NTRS1993

A fixed/variable bit-rate data compression architecture

A VLSI architecture for an adaptive data compression encoder capable of sustaining fixed or variable bit-rate output has been developed. There are three modes of operation: lossless with variable bit-rate, lossy with fixed bit-rate and lossy with variable bit-rate. For lossless encoding, the implementation is identical to the USES chip designed for Landsat 7. Obtaining a fixed bit-rate is achieved with a lossy DPCM algorithm using adaptive, nonuniform scalar quantization. In lossy mode, variable bit-rate coding uses the lossless sections of the encoder for post-DPCM entropy coding. The encoder shows excellent compression performance in comparison to other current data compression techniques. No external tables or memory are required for operation.

Zweigle, Gregary C.↗
NASA NTRS1992

Critical early mission design considerations for lunar data systems architecture

This paper outlines recent early mission design activites for a lunar data systems architecture. Each major functional element is shown to be strikingly similar when viewed in a common reference system. While this similarity probably deviates with lower levels of decomposition, the sub-functions can always be arranged into similar and dissimilar categories. Similar functions can be implemented as objects - implemented once and reused several times like today's advanced integrated circuits. This approach to mission data systems, applied to other NASA programs, may result in substantial agency implementation and maintenance savings. In today's zero-sum-game budgetary environment, this approach could help to enable a lunar exploration program in the next decade. Several early mission studies leading to such an object-oriented data systems design are recommended.

Hei, Donald J., Jr.↗
NASA NTRS2018

Kepler Data Validation I: Architecture, Diagnostic Tests, and Data Products for Vetting Transiting Planet Candidates

The Kepler Mission was designed to identify and characterize transiting planets in the Kepler Field of View and to determine their occurrence rates. Emphasis was placed on identification of Earth-size planets orbiting in the Habitable Zone of their host stars. Science data were acquired for a period of four years. Long-cadence data with 29.4 min sampling were obtained for approx. 200,000 individual stellar targets in at least one observing quarter in the primary Kepler Mission. Light curves for target stars are extracted in the Kepler Science Data Processing Pipeline, and are searched for transiting planet signatures. A Threshold Crossing Event is generated in the transit search for targets where the transit detection threshold is exceeded and transit consistency checks are satisfied. These targets are subjected to further scrutiny in the Data Validation (DV) component of the Pipeline. Transiting planet candidates are characterized in DV, and light curves are searched for additional planets after transit signatures are modeled and removed. A suite of diagnostic tests is performed on all candidates to aid in discrimination between genuine transiting planets and instrumental or astrophysical false positives. Data products are generated per target and planet candidate to document and display transiting planet model fit and diagnostic test results. These products are exported to the Exoplanet Archive at the NASA Exoplanet Science Institute, and are available to the community. We describe the DV architecture and diagnostic tests, and provide a brief overview of the data products. Transiting planet modeling and the search for multiple planets on individual targets are described in a companion paper. The final revision of the Kepler Pipeline code base is available to the general public through GitHub. The Kepler Pipeline has also been modified to support the Transiting Exoplanet Survey Satellite (TESS) Mission which is expected to commence in 2018.

data analysis↗
NASA NTRSDate not supplied

System Architecture and Data Transfers

This presentation is an overview of the NASA UTM Project’s efforts on the architecture and data exchanges related to UTM. It covers the evolution of the overall system, a walk through of the current architecture, a summary of impacts of the work, and several references to relevant UTM publications.

UTM↗