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50 records · Page 3

Dual-polarization O-band silicon photonics transmitter with an integrated tunable laser, Mach-Zehnder modulators, and SOAs

Presented is an O-band silicon photonics dual-polarization coherent/IMDD modulator integrated with semiconductor optical amplifiers and tunable laser to enhance the short-reach link budget. The laser demonstrated output power >6 dBm and a <250 kHz linewidth over a 14 nm tuning range. Modulators paired with custom 64 Gbaud QPSK drivers exhibited improved analog link sensitivity compared to similar devices without integrated gain sections. They also demonstrated 53 Gbaud dual-polarization PAM4 operation when characterized with a linear driver and MaxLinear 100G/lane DSP board. Both optical links achieved BERs at the KP4-FEC threshold and overall transmitter assembly energy consumption <6.9 pJ/bit without any thermal control when at steady room temperatures.

Liu, Junqian (ORCID:0000000167337650)↗

Enter the AHU (36th Chamber of ASHRAE): A Multi-site Field Study of ASHRAE G36

Despite being recognized as the best practice for advanced building controls, ASHRAE Guideline 36 (G36) has seen slow adoption in retrofit cases. Decisionmakers lack credible field evidence to justify the time and person-power investment. Most prior analyses have relied on software simulations, which overlook implementation challenges and fail to persuade owners to move from models to real-world deployment. This paper presents a multi-site field study of G36 performance, drawing on measured results from 17 projects across diverse building types and climate zones. The analysis disaggregates outcomes by the most widely adopted air handling unit (AHU) based G36 strategies, including trim-and-respond approaches to supply air temperature (SAT) and duct static pressure (DSP) reset, and economizer controls. Results for controls re programming implementations are encouraging, with HVAC savings ranging from 2% - 49%, with a median of 18%. The range aligns with simulation study findings showing 1% - 46% savings through these three strategies. These findings show that even without capital investment in control infrastructure upgrades, existing building owners are reaping significant benefits from updating HVAC sequences of operation to industry best-practice solutions. The results give practitioners and decisionmakers a reference point on what to expect, which strategies deliver, and how field performance may compare to simulation.

Deshpande, Reva↗

Next-Generation Modular Flexible Low-Cost SiC-based High-Frequency-Link Transformer (Final Technical Report)

This project, led by the small business NextWatt LLC, led to the design and development of a novel high-frequency-link (HFL) transformer that yields reduce number of semiconductor devices compared to conventional solid-state transformers (SSTs). The HFL transformer is based on SiC device technology and nanocrystalline-core-based magnetics techniology. The control actuation of the SiC devices are algorithmically implemented in digital signal processor (DSP) platform. The overall HFL transformer technology is conceived and developed using a modular approach. During the course of the project the novel technology and its experimental performances at the module, multi-phase, and cascaded multi-phase levels have been demonstrated to the sponsor U.S. Department of Energy (DOE).

24 POWER TRANSMISSION AND DISTRIBUTION↗

Digital Signal Processing Using Deep Neural Networks

Currently there is great interest in the utility of deep neural networks (DNNs) for the physical layer of radio frequency (RF) communications. In this manuscript we describe a custom DNN specially designed to solve problems in the RF domain. Our model leverages the mechanisms of feature extraction and attention through the combination of an autoencoder convolutional network with a transformer network, to accomplish several important communications network and digital signals processing (DSP) tasks. We also present a new open dataset and physical data augmentation model that enables training of DNNs that can perform automatic modulation classification, infer, and correct transmission channel effects, and directly demodulate baseband RF signals.

42 ENGINEERING↗

Evolution of the electrothermal instability from thick rod z pinches subject to dynamically and statically applied axial magnetic field

LDRD Project 229427 aimed to determine how electrothermal instability (ETI) driven heating on a z-pinch rod pulsed with intense current evolves under mixed magnetic field (azimuthal + axial) conditions, which is pertinent to pulsed-power-driven magnetically-insulated transmission lines and physics targets. Experiments focused on diagnosing ETI-driven heating from deliberately-machined and well-characterized micron-scale surface defects (referred to as engineered defects or ED). Prior to the start of this project, understanding of how unmagnetized (B z =0) ED evolve had been obtained—simulations largely reproduce the experimentally observed high temperature spots which develop at the poles of bare/uncoated ED. Project 229427 extended the Mykonos Facility ED experimental platform to include axial field. In the first class of experiments, axial field was provided “dynamically” via a helical return can (HRC). In this case, B z and B θ rise at the same rate. Generally, the HRC generated magnetic field at a fixed polarization angle Φ B =arctan(B z /B θ )=15° on the rod's surface. In the second class of experiments, axial field was provided “statically” via a slow-rising (millisecond) external Helmholtz coil pair. In this case, B z was effectively constant/static throughout the 100 ns rise of the Mykonos current. For either case, a primary goal was to determine whether ETI provides a helical seed perturbation for the subsequent growth of the helical magneto Rayleigh-Taylor modes observed in MagLIF (static B z ) and dynamic screw pinch (DSP, dynamic B z ) experiments. When dynamic field was applied using an HRC, emissions from individual ED aligned toward Φ B , while emissions from ED within pairs elongated and preferentially merged along Φ B . These data strongly support that for a randomized defect distribution, heating from nearby current-density perturbations will favorably merge about Φ B to generate an extended seed perturbation that aligns toward the surface-field polarization, and this may impact the orientation of subsequent MRT growth on imploding liners. The results from the static field experiments were largely inconclusive, as any ETI heating rotation, if present, was obscured/overwhelmed by local/random heating from ED rim imperfections.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

Rapid Inference of Logic Gate Neural Networks for Anomaly Detection in High Energy Physics

The increasing data rates and complexity of detectors at the Large Hadron Collider (LHC) necessitate fast and efficient machine learning models, particularly for rapid selection of what data to store, known as triggering. Building on recent work in differentiable logic gates, we present a public implementation of a Convolutional Differentiable Logic Gate Neural Network (CLGN). We apply this to detecting anomalies at the Level-1 Trigger at CMS using public data from the CICADA project. We demonstrate that the CLGN achieves physics performance on par with or superior to conventional quantized neural networks. We also synthesize an LGN for a Field-Programmable Gate Array (FPGA) and show highly promising FPGA characteristics, notably zero Digital Signal Processor (DSP) resource usage. This work highlights the potential of logic gate networks for high-speed, on-detector inference in High Energy Physics and beyond.

FOS: Physical sciences↗

Obvious and non-obvious aspects of digital Self-Excited-Loops for SRF cavity control

In 1978, Delayen showed how Self-Excited Loops (SEL) can be used to great advantage for controlling narrow-band SRF cavities. Its key capability is establishing closed-loop amplitude control early in the setup process, stabilizing Lorentz forces to allow cavity tuning and phase loop setup in a stable environment. As people around the world implement this basic idea with modern FPGA DSP technology, multiple variations and operational scenarios creep in that have both obvious and non-obvious ramifications for latency, feedback stability, and resiliency. This paper will review the key properties of a Delayen-style SEL when set up for open-loop, amplitude stabilized, and phase-stabilized modes. Then the original analog circuit will be compared and contrasted with the known variations of digital CORDIC-based implementations.

Doolittle, Larry [LBL, Berkeley]↗

Simple and Robust Carrier-Based PWM Technique for Single-Stage Three-phase Rectifier Indirect Matrix Converter

Indirect matrix converters (IMC) can offer high efficiency, high power density, and bidirectional power flow capability with a single-stage three-to single-phase AC-AC power conversion integrating a conventional three-phase active rectifier with a primary side full-bridge inverter of a dual active bridge converter. However, the IMCs generally require space vector modulation techniques, leading to complex sectors and dwell times calculations. A practical implementation of the modulation methods with a commonly used digital signal processor becomes even more challenging when considering power factor correction, harmonics reduction, and deadtime between sector transitions. This paper proposes a simple and robust carrier-based pulse width modulation (PWM) technique determined through a voltage-source inverter (VSI) to current-source inverter (CSI) to IMC conversion. This translation enables the adoption of all conventional VSI control methods with active and reactive power control in the IMCs through simple carrier and reference waveform comparison. The VSI vectors are first one-on-one matched with CSI vectors and translated to IMC modulation signals without calculating sectors and dwell times. Nine different carrier waveforms are proposed, and the converter performance is analyzed. Grid current THD and efficiency are estimated for each modulation method. The symmetric A and B methods had the lowest THD of the grid current, 2.80%, and the efficiency remained at approximately 98.3%, making it the most suitable carrier-based method proposed in this paper. The space vector PWM (SVPWM) modulation method was implemented to the DSP and generated the expected twelve gate signals.

Benson, Mikayla↗

The level-1 trigger for the SuperCDMS experiment at SNOLAB

The SuperCDMS SNOLAB dark matter search experiment aims to be sensitive to energy depositions down to Script O(1 eV). This imposes requirements on the resolution, signal efficiency, and noise rejection of the trigger system. To accomplish this, the SuperCDMS level-1 trigger system is implemented in an FPGA on a custom PCB. A time-domain optimal filter algorithm realized as a finite impulse response filter provides a baseline resolution of 0.38 times the standard deviation of the noise, σn, and a 99.9% trigger efficiency for signal amplitudes of 1.1 σ n in typical noise conditions. Embedded in a modular architecture, flexible trigger logic enables reliable triggering and vetoing in a dead-time-free manner for a variety of purposes and run conditions. The trigger architecture and performance are detailed in this article.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

A Low-Power 1 Gb/s Line Driver with Configurable Pre-Emphasis for Lossy Transmission Lines

A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated (SST) drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.

47 OTHER INSTRUMENTATION↗

Signal processing to reduce dark noise impact in precision timing

We introduce a technique to mitigate the effects of low frequency noise on precision timing. The example of Dark Count Noise Rate (DCR) in Silicon Photomultipliers (SiPMs) is emphasized. This technique exploits the correlation between time shifts on the leading edge of a signal and the residual slope of the baseline (due to noise) which remains after baseline subtraction. In fast timing applications (such as for Time-of-flight particle ID) the signal arrival time is typically captured on the signal leading edge. The signal risetime is often fixed by the physics of the sensor and input circuit. Then accurate pulse timing can be achieved by correcting a leading edge threshold time (depending on a slope proportional to both the Amplitude and the risetime) to a “constant fraction” time. This compensation for time walk due to amplitude fluctuations breaks down once we introduce interference from low frequency noise on the leading edge. In this paper we demonstrate that an additional measurement of the slope at threshold can be used to correct for this noise jitter.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Low power on-chip data transmission for wafer-scale monolithic active pixel sensors

Here, this paper details the implementation of the digital pulse shaping subsystem within the Backbone Transmission Line Encoding (BTLE) driver, a low-power, long-distance on-chip data transmission solution designed in a 65 nm CMOS process. Digital pulse shaping is critical for minimizing inter-symbol interference (ISI) caused by bandwidth limitations of on-chip interconnects, especially in wafer-scale monolithic active pixel sensors (MAPS). A duobinary encoder coupled with a parallelized polyphase finite impulse response (FIR) filter is used for efficient shaping of the transmitted signal spectrum. This reconfigurable architecture achieves reliable 160 Mb/s data transfer over a 10 cm on-chip link, as validated by simulations demonstrating low power consumption (FoM 37.3 fJ/bit/mm of transmission line length) and effective ISI mitigation.

47 OTHER INSTRUMENTATION↗

Large-scale real-time signal processing in physics experiments: the ALICE TPC FPGA pipeline

For LHC Run 3, the ALICE Time Projection Chamber was upgraded to operate in continuous readout mode. Interaction rates of up to 50 kHz in Pb-Pb collisions require real-time processing of more than 3 TB s -1 of raw detector data. This requirement is met by a custom FPGA-based processing pipeline that performs the complete front-end data treatment fully in-stream, including common-mode correction, pedestal subtraction, ion-tail filtering, zero suppression, and dense data packing. A central element of the design is a highly parallel common-mode correction algorithm operating directly on the streaming data. It robustly identifies signal-free readout channels on a time-bin basis and applies pad-dependent scaling to compensate for local variations in capacitive coupling in the GEM readout. In combination with pedestal subtraction and ion-tail filtering, this enables accurate baseline restoration under extreme high-occupancy conditions, preventing signal loss while efficiently suppressing noise prior to zero suppression. The pipeline operates continuously at the full detector bandwidth and reduces the raw input rate of approximately 3 TB s -1 to about 900 GBps for Pb-Pb collisions at the target interaction rate. Overall, it represents a large-scale FPGA-based real-time signal-processing implementation for high-energy physics detector readout.

Digital signal processing (DSP)↗