Static Reuse Profile Estimation for Array-based Applications
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Computer Hardware↗
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Trilinos: Enabling Scientific Computing across Diverse Hardware Architectures at Scale
Trilinos is a community-developed, open-source software framework that facilitates building large-scale, complex, multiscale, multiphysics simulation code bases for scientific and engineering problems. Since the Trilinos framework has undergone substantial changes to support new applications and new hardware architectures, this document is an update to “An Overview of the Trilinos project” by Heroux et al. (ACM Transactions on Mathematical Software, 31(3):397–423, 2005). It describes the design of Trilinos, introduces its new organization in product areas, and highlights established and new features available in Trilinos. Particular focus is put on the modernized software stack based on the Kokkos ecosystem to deliver performance portability across heterogeneous hardware architectures. This article also outlines the organization of the Trilinos community and the contribution model to help onboard interested users and contributors.
Heterogeneous Hardware Architectures↗
Energy Efficient Probabilistic Scientific Computing on Neuromorphic Hardware
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Smith, John Darby↗
Dynamic, symmetry-preserving, and hardware-adaptable circuits for quantum computing many-body states and correlators of the Anderson impurity model
We present a hardware-reconfigurable ansatz on N q -qubits for the variational preparation of many-body states of the Anderson impurity model (AIM) with N imp + N bath = N q /2 sites, which conserves total charge and spin z component within each variational search subspace. The many-body ground state of the AIM is determined as the minimum over all minima of O(N$^2_ q$) distinct charge-spin sectors. Hamiltonian expectation values are shown to require ω(N q ) < N meas. $\leqslant$ O(N imp N bath ) symmetry-preserving, parallelizable measurement circuits, each amenable to postselection. To obtain the one-particle impurity Green’s function we show how initial Krylov vectors can be computed via midcircuit measurement and how Lanczos iterations can be computed using the symmetry-preserving ansatz. For a single-impurity Anderson model with a number of bath sites increasing from one to seven, we show using numerical emulation that the ease of variational ground-state preparation is suggestive of linear scaling in circuit depth and subquartic scaling in optimizer complexity. We therefore expect that, combined with time-dependent methods for Green’s function computation, our ansatz provides a useful tool to account for electronic correlations on early fault-tolerant processors. Finally, with a view towards computing real materials properties of interest like magnetic susceptibilities and electron-hole propagators, we provide a straightforward method to compute many-body, time-dependent correlation functions using a combination of time evolution, midcircuit measurement-conditioned operations, and the Hadamard test.
36 MATERIALS SCIENCE↗
Quantum algorithm for polaritonic chemistry based on an exact ansatz
Abstract Cavity-modified chemistry uses strong light-matter interactions to modify the electronic properties of molecules in order to enable new physical phenomena such as novel reaction pathways. As cavity chemistry often involves critical regions where configurations become nearly degenerate, the ability to treat multireference problems is crucial to understanding polaritonic systems. In this Letter, we show through the use of a unitary ansatz derived from the anti-Hermitian contracted Schrödinger equation that cavity-modified systems with strong correlation, such as the deformation of rectangular H 4 coupled to a cavity mode, can be solved efficiently and accurately on a quantum device. In contrast, while our quantum algorithm can be made formally exact, classical-computing methods as well as other quantum-computing algorithms often yield answers that are both quantitatively and qualitatively incorrect. Additionally, we demonstrate the current feasibility of the algorithm on near intermediate-scale quantum hardware by computing the dissociation curve of H 2 strongly coupled to a bosonic bath.
Warren, Samuel (ORCID:0000000157134454)↗
Remote operation of the DIII-D National Fusion Facility
Abstract Full remote scientific operation of the DIII-D National Fusion Facility is now possible through significant advances in the computer science hardware and software infrastructure made over the last decade. Capabilities around information visualization, data movement, and communication have all been enhanced. The level of capability deployed to remotely operate DIII-D required an infrastructure advancement over what had previously been achieved in the fusion community. The large quantity of real-time data that is automatically displayed on DIII-D’s control room screens can now be visualized by remote participants via web-based applications. New audio/video solutions using the VoIP and instant messaging application Discord have been implemented to mimic the dynamic and ad-hoc scientific conversations that are critical in successfully operating an experimental campaign. Discord’s ability for a user to rapidly move between audio channels, text with images, and share screens is a significant enhancement over traditional videoconferencing tools. In addition, multiple combinations of broadcast audio are made available via a web-based application to allow remote participants to simultaneously listen to general announcements/sounds while conducting their own specific conversations. Secure methodologies have been put into place to allow remote control of hardware including DIII-D’s plasma control system application. Secure methods also included the ability of the on-site team to closely coordinate their work with remote team members which has been enhanced through extensions to the wireless network and the use of tablet computers for audio/video/screen sharing. However, no amount of software can fully replace the need for ‘hands on hardware.’ This infrastructure was severely stress tested during the COVID-19 pandemic where occupancy of the DIII-D control room was restricted. Operational efficiency during the pandemic, measured in discharges per hour, remained high (3.8 ± 0.8) compared to values obtained pre-pandemic (3.7 ± 0.8).
70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
Quantum Circuit Cutting for Classical Shadows
Classical shadow tomography is a sample-efficient technique for characterizing quantum systems and predicting many of their properties. Circuit cutting is a technique for dividing large quantum circuits into smaller fragments that can be executed more robustly using fewer quantum resources. We introduce a divide-and-conquer circuit cutting method for estimating the expectation values of observables using classical shadows. We derive a general formula for making predictions using the classical shadows of circuit fragments from arbitrarily cut circuits and provide the sample complexity analysis for the case when observables factorize across fragments. Then, we numerically show that our divide-and-conquer method outperforms traditional uncut shadow tomography when estimating high-weight observables that act non-trivially on many qubits and discuss the mechanisms for this advantage.
97 MATHEMATICS AND COMPUTING↗
Nature-GL: A Revolutionary Learning Paradigm Unleashing Nature’s Power in Real-World Spatial-Temporal Graph Learning
Spatial-Temporal Graph Learning (ST-GL) is a prominent research area due to its unique capability to effectively learn real-world graphs. Applications of ST-GL pose stringent and various demands on not only real-time inference with low energy cost and high ac- curacy but also fast training. Unfortunately, as Moore’s Law approaches its limits and ST-GL model complexity drastically grows, the gap between digital hardware’s computational power and ST- GL application demands is widening. In response, this paper introduces Nature-GL, a nature-powered graph learning paradigm that exploits the principle of entropy increase to advance graph learning. In particular, Nature-GL transforms both the training and inference of real-valued ST-GL into electron-speed natural anneal- ing processes of a parameterized dynamical system that represents the target graphs. Experimental results across four real-world ap- plications with six datasets demonstrate that Nature-GL achieves orders-of-magnitude speedups in both training and inference, delivering higher accuracy compared to Graph Neural Networks.
Liu, Chuan [University of Rochester]↗
HDBind: encoding of molecular structure with hyperdimensional binary representations
Traditional methods for identifying “hit” molecules from a large collection of potential drug-like candidates rely on biophysical theory to compute approximations to the Gibbs free energy of the binding interaction between the drug and its protein target. These approaches have a significant limitation in that they require exceptional computing capabilities for even relatively small collections of molecules. Increasingly large and complex state-of-the-art deep learning approaches have gained popularity with the promise to improve the productivity of drug design, notorious for its numerous failures. However, as deep learning models increase in their size and complexity, their acceleration at the hardware level becomes more challenging. Hyperdimensional Computing (HDC) has recently gained attention in the computer hardware community due to its algorithmic simplicity relative to deep learning approaches. The HDC learning paradigm, which represents data with high-dimension binary vectors, allows the use of low-precision binary vector arithmetic to create models of the data that can be learned without the need for the gradient-based optimization required in many conventional machine learning and deep learning methods. This algorithmic simplicity allows for acceleration in hardware that has been previously demonstrated in a range of application areas (computer vision, bioinformatics, mass spectrometery, remote sensing, edge devices, etc.). To the best of our knowledge, our work is the first to consider HDC for the task of fast and efficient screening of modern drug-like compound libraries. We also propose the first HDC graph-based encoding methods for molecular data, demonstrating consistent and substantial improvement over previous work. We compare our approaches to alternative approaches on the well-studied MoleculeNet dataset and the recently proposed LIT-PCBA dataset derived from high quality PubChem assays. We demonstrate our methods on multiple target hardware platforms, including Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs), showing at least an order of magnitude improvement in energy efficiency versus even our smallest neural network baseline model with a single hidden layer. Our work thus motivates further investigation into molecular representation learning to develop ultra-efficient pre-screening tools. We make our code publicly available at https://github.com/LLNL/hdbind.
59 BASIC BIOLOGICAL SCIENCES↗
Energy Efficient Scientific Computing with Probabilistic Algorithms on Neuromorphic Hardware
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Smith, John Darby↗
Even Higher-Level Synthesis: An Exploration of AI Hardware Accelerators using HLS4ML
With the rise of artificial intelligence, the popularization of deep learning, and a constantly evolving industry, the demand for flexible and efficient tools has never been greater. As algorithms grow more complex, their runtime and energy consumption increase exponentially. Customized hardware accelerators, long used for specific mathematical operations, remain essential for managing modern applications' computational and power demands. Hardware accelerators can speed up complex computations by orders of magnitude, but their manual design and verification processes are often challenging and time-consuming. High-Level Synthesis (HLS) provides a solution by transforming high-level algorithm descriptions, typically written in C++ or SystemC, into synthesizable RTL suitable for hardware implementation. This approach reduces development time for RTL engineers while offering flexibility beyond what traditional handwritten RTL can provide. We extended this capability to the machine-learning domain with the open-source framework hls4ml, which allows neural networks trained in Python frameworks like Tensorflow or PyTorch to be synthesized into efficient hardware representations for the traditional FPGA and ASIC flows. This breakthrough addresses the growing need for reduced design turnaround and easy verification of ML hardware accelerators with low latency and power efficiency constraints. During this tutorial, we will demonstrate how Python complements HLS by simplifying the ML design process, bridging the gap between software and hardware development. Attendees will explore how we translate neural networks modeled in Python into fixed-point C++ models suitable for HLS workflows. We will dive into strategies like Value-Range Analysis and Quantization-Aware Training, which optimize these designs for deployment and evaluate their accuracy, power consumption, and energy efficiency. To exemplify these concepts, experts from Fermilab will share their experiences applying this technology to high-energy physics experiments, where real-time, low-latency processing is critical. Over the years, Fermilab engineers have demonstrated how deep neural networks, optimized for hardware using hls4ml, can meet the stringent requirements of trigger systems at the CERN Large Hadron Collider. These systems rely on rapid decision-making to process immense data volumes while retaining only the most relevant events for further analysis. The application of hls4ml has also been extended to innovative technologies like smart pixel arrays. These smart pixels integrate ML inference capabilities directly into sensor devices, enabling localized data processing at the pixel level. This approach drastically reduces the need to transmit raw data to external processing units, significantly decreasing power consumption and latency. By embedding neural networks within the pixel architecture, the smart pixels can identify and prioritize relevant data in real time, providing a highly efficient solution for edge computing in scenarios such as particle detectors and imaging systems. Fermilab's work highlights the potential of hardware-accelerated ML in scenarios where both speed and power efficiency are mission-critical. Through this tutorial, attendees will gain valuable insights into the challenges and solutions of deploying ML in hardware. Understanding how HLS and hls4ml streamline the development of neural network-based hardware accelerators is fundamental for the industry's future. Participants will learn how these technologies are shaping the future of AI and scientific computing.
Di Guglielmo, Giuseppe [Fermilab]↗
SECURED: Simulator-Enhanced Control and Understanding of Reactor systems for cyber-Event Defense
The study discusses a learning approach for analyzing cyber-events in reactor systems using integrated hardware and personal computer simulator models. Key points include the rise in cyber-attacks and their sophistication in industrial control systems (ICS), the necessity for awareness, understanding, resource allocation, and preparation to combat these threats, and the digital transformation of old and new nuclear plants, increasing their exposure to cyber threats. It highlights the cyber vulnerabilities of advanced reactor systems, which rely on digital instrumentation and control for operations and safety functions, making them susceptible to cyber-attacks. The approach involves demonstrating reactor system plant ICS cyber-attacks under various operational conditions utilizing tools like simulator models and hardware-based kits. A strategic solution approach tailored to critical infrastructure is emphasized, along with community engagement for public and government support, adopting effective learning approaches, and the preparation for anticipated future challenges. The presentation concludes with a call to action to address challenges, leverage opportunities, and advance through lesson learning in cybersecurity for nuclear energy systems.
21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗
Surrogate Neural Architecture Codesign Package (SNAC-Pack)
Neural architecture search (NAS) is a powerful approach for automating model design, but existing methods often optimize for accuracy alone or rely on proxy metrics such as bit operations (BOPs) that correlate poorly with hardware cost. This gap is particularly large for FPGA deployment, where cost is dominated by a multi-dimensional budget of lookup tables, DSPs, flip-flops, BRAM, and latency. We present the Surrogate Neural Architecture Codesign Package (SNAC-Pack), an open-source AutoML framework for hardware-aware neural architecture codesign and end-to-end FPGA deployment. SNAC-Pack runs a multi-objective global search with Optuna and NSGA-II, loading trials to a shared SQLite store that enables parallel workers across compute nodes. A hardware surrogate model outputs per-trial resource and latency estimates, avoiding the synthesis cost that would otherwise dominate the search loop. A local search stage then applies quantization-aware training (QAT) together with iterative magnitude pruning in a combined compression loop, after which the final model is synthesized to FPGA firmware via the hls4ml Python library. A YAML configuration and an optional agentic frontend let users run the pipeline on new datasets without modifying the framework. We demonstrate SNAC-Pack on jet classification at the Large Hadron Collider and superconducting qubit readout, discovering compact architectures that match or exceed strong baselines on the task metric while reducing FPGA resource utilization and, in the qubit readout case, reducing the design space exploration process from months of manual fine-tuning to hours of automated search.
Weitz, Jason [UC, San Diego]↗
Sentinel
Network intrusion detection systems (NIDS) are commonplace in network security but they frequently employ algorithms that are computational demanding requiring hardware and software with significant power requirements. Two examples of such resource-intensive algorithms used for network security are regular expression matching and broader signature pattern matching which are commonly used in deep packet inspection (DPI). Network security algorithms that have large power requirements may be a challenge for low-power internet-of-things (IoT) environments, which generally lack the power resources to implement complex security measures like computationally expensive DPI at the edge. Furthermore, IoT environments incorporating 5G standalone networks have network latency constraints beyond just power that make DPI at the edge even more difficult. Programmable logic is ideally suited for machine learning inference for DPI because of its deep instruction level parallelism and single-cycle memory access. Machine learning approaches for DPI have been explored before using the programmable logic of field programmable gate arrays (FPGA) as a potential solution for NIDS approaches that would be power-suitable for IoT. However, those previous programmable logic NIDS approaches utilize either a supervised or unsupervised learning model. Sentinel utilizes the ensemble of these two machine learning approaches known as a semi-supervised approach which has shown promise in NIDS implementations. Sentinel provides a programmable logic implementation of a semi-supervised approach for DPI which operates at much lower power and latency than a GPU implementation with negligible loss of accuracy due to quantization through a logistic regressor.
Anderson, MatthewW [Idaho National Laboratory (INL↗
LuGo: An enhanced quantum phase estimation implementation
Quantum Phase Estimation (QPE) is a cardinal algorithm in quantum computing that plays a crucial role in various applications, including cryptography, molecular simulation, and solving systems of linear equations. However, the standard implementation of QPE faces challenges related to time complexity and circuit depth, which limit its practicality for large-scale computations. We introduce LuGo, a novel framework designed to enhance the performance of QPE by reducing circuit duplication, as well as using parallelization techniques to achieve faster generation of the QPE circuit and gate reduction. We validate the effectiveness of our framework by generating quantum linear solver circuits, which require both QPE and inverse QPE, to solve linear systems of equations. LuGo achieves significant improvements in both computational efficiency and hardware requirements without compromising on accuracy. Compared to a standard QPE implementation, LuGo reduces time consumption to generate a circuit that solves a 2 6 × 2 6 system matrix by a factor of 50.68 and over 31× reduction of quantum gates and circuit depth, with no fidelity loss on an ideal quantum simulator. Furthermore, we demonstrated the versatility and scalability of LuGo enabled HHL algorithm by simulating a canonical Hele-Shaw fluid problem using a quantum simulator. With these advantages, LuGo paves the way for more efficient implementations of QPE, enabling broader applications across several quantum computing domains.
Quantum algorithm↗
Syncopated dynamical decoupling to suppress crosstalk in quantum circuits
Theoretically understanding and experimentally characterizing and modifying the underlying Hamiltonian of a quantum system is of utmost importance in achieving high-fidelity quantum gates for quantum computing. Here, in this work, we explore the use of dynamical decoupling (DD) in characterizing and suppressing undesired two-qubit couplings as well as the underlying single-qubit decoherence, both significant hurdles to achieving precise quantum control and realizing quantum computing on many hardware prototypes. Through discrete search of DD sequences, we identify sequences that protect against decoherence and selectively target unwanted two-qubit interactions of general form. On a transmon-qubit-based superconducting quantum device, we identify separate white and 1/𝑓 noise components underlying the single-qubit decoherence and a static ZZ coupling between pairs of qubits. A family of syncopated DD sequences is found and their efficiency is demonstrated in two-qubit benchmarking experiments. The syncopated decoupling technique significantly boosts performance in a realistic algorithmic quantum circuit.
97 MATHEMATICS AND COMPUTING↗
A parametrically programmable delay line for microwave photons
Delay lines that store quantum information are crucial for advancing quantum repeaters and hardware efficient quantum computers. Traditionally, they are realized as extended systems that support wave propagation but provide limited control over the propagating fields. Here, we introduce a parametrically addressed delay line for microwave photons that provides a high level of control over the stored pulses. By parametrically driving a three-wave mixing circuit element that is weakly hybridized with an ensemble of resonators, we engineer a spectral response that simulates that of a physical delay line, while providing fast control over the delay line’s properties. We demonstrate this novel degree of control by choosing which photon echo to emit, translating pulses in time, and even swapping two pulses, all with pulse energies on the order of a single photon. We also measure the noise added from our parametric interactions and find it is much less than one photon.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Advantages of imperfect dice rolls over coin flips for random number generation
With an eye toward neural-inspired probabilistic computation, recent work has examined the development of true random number generators via stochastic devices. Typically, these devices are operated in a two-state regime to produce a sequence of binary outcomes (i.e., coin flips). However, there is no guarantee that stochastic devices will infallibly produce fair outputs and small deviations from a uniform distribution may have unwanted complications in applications. Using mathematical analysis, we contend that opting instead for a multi-state device (i.e., a dice roll) has benefits in these unfair paradigms. To demonstrate these benefits, we apply this framework to the analysis of a tunnel diode operated in a stochastic regime. In particular, interpreting the binary stochastic output of the tunnel diode as a multi-state die roll output also sees advantages in remaining closer to uniform. Overall, our approach provides a compelling argument for mathematical driven co-design and development of novel probabilistic computing devices and hardware.
applied mathematics↗