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Tough Errors are no Match (TEAM): Optimizing the Quantum Compiler for Noise Resilience

This project builds toward a comprehensive error-mitigating toolkit that makes quantum programming more robust and adaptive to the noisy, resource-limited nature of today’s quantum hardware. To that end, it integrates established error-mitigation methods — such as zero-noise extrapolation and dynamical decoupling — directly into compiler infrastructures. These techniques will be packaged as modules that can automatically adjust and combine based on performance analysis, enabling compilers to explore large design spaces and produce optimized, low-noise quantum programs with minimal manual intervention. In parallel, this project also explores new approaches to analog quantum programming or quantum simulation, and has developed the programming language SimuQ which treats quantum Hamiltonian evolution as the central object.

97 MATHEMATICS AND COMPUTING↗

Tough Errors Are no Match (TEAM): Optimizing the quantum compiler for noise resilience

This report summarizes Unitary Fund’s contributions to the Department of Energy’s TEAM project (DE-SC0020266) under Thrust 2: Quantum Programming and Compilation. The central outcomes of this work have been the development of Mitiq, an open-source Python toolkit for applying quantum error mitigation (QEM) techniques to noisy quantum programs, and the invention, benchmarking and theoretical investigation of novel QEM techniques. Additional outcomes include the development of other open source software packages for the usage, simulation and control of quantum computers.

97 MATHEMATICS AND COMPUTING↗

Tough Errors are no Match (TEAM): Optimizing the Quantum Compiler for Noise Resilience

This report summarizes our contributions to the Department of Energy’s Tough Errors are no Match (TEAM) project (DE-SC0020377) under Thrust 2: Quantum Programming and Compilation. The central outcomes of this work included a novel efficient quantum compiling algorithm which works without requiring the quantum computer to exactly invert its operations, answering a longstanding open problem in quantum compiling. Additional results include the implementation of zero-noise extrapolation error mitigation in collaboration with the Unitary Fund, as well as novel quantum algorithms for entanglement detection and pseudorandomness.

Bouland, Adam [Stanford Univ., CA (United States)]↗

TU-AB-BRC-12: Optimized Parallel MonteCarlo Dose Calculations for Secondary MU Checks

Purpose: Secondary MU checks are an important tool used during a physics review of a treatment plan. Commercial software packages offer varying degrees of theoretical dose calculation accuracy, depending on the modality involved. Dose calculations of VMAT plans are especially prone to error due to the large approximations involved. Monte Carlo (MC) methods are not commonly used due to their long run times. We investigated two methods to increase the computational efficiency of MC dose simulations with the BEAMnrc code. Distributed computing resources, along with optimized code compilation, will allow for accurate and efficient VMAT dose calculations. Methods: The BEAMnrc package was installed on a high performance computing cluster accessible to our clinic. MATLAB and PYTHON scripts were developed to convert a clinical VMAT DICOM plan into BEAMnrc input files. The BEAMnrc installation was optimized by running the VMAT simulations through profiling tools which indicated the behavior of the constituent routines in the code, e.g. the bremsstrahlung splitting routine, and the specified random number generator. This information aided in determining the most efficient compiling parallel configuration for the specific CPU’s available on our cluster, resulting in the fastest VMAT simulation times. Our method was evaluated with calculations involving 10{sup 8} – 10{sup 9} particle histories which are sufficient to verify patient dose using VMAT. Results: Parallelization allowed the calculation of patient dose on the order of 10 – 15 hours with 100 parallel jobs. Due to the compiler optimization process, further speed increases of 23% were achieved when compared with the open-source compiler BEAMnrc packages. Conclusion: Analysis of the BEAMnrc code allowed us to optimize the compiler configuration for VMAT dose calculations. In future work, the optimized MC code, in conjunction with the parallel processing capabilities of BEAMnrc, will be applied to provide accurate and efficient secondary MU checks.

60 APPLIED LIFE SCIENCES↗

Optimizing adiabatic quantum program compilation using a graph-theoretic framework

Adiabatic quantum computing has evolved in recent years from a theoretical field into an immensely practical area, a change partially sparked by D-Wave System’s quantum annealing hardware. These multimillion-dollar quantum annealers offer the potential to solve optimization problems millions of times faster than classical heuristics, prompting researchers at Google, NASA and Lockheed Martin to study how these computers can be applied to complex real-world problems such as NASA rover missions. Unfortunately, compiling (embedding) an optimization problem into the annealing hardware is itself a difficult optimization problem and a major bottleneck currently preventing widespread adoption. Additionally, while finding a single embedding is difficult, no generalized method is known for tuning embeddings to use minimal hardware resources. To address these barriers, we introduce a graph-theoretic framework for developing structured embedding algorithms. Using this framework, we introduce a biclique virtual hardware layer to provide a simplified interface to the physical hardware. Additionally, we exploit bipartite structure in quantum programs using odd cycle transversal (OCT) decompositions. By coupling an OCT-based embedding algorithm with new, generalized reduction methods, we develop a new baseline for embedding a wide range of optimization problems into fault-free D-Wave annealing hardware. Furthermore, to encourage the reuse and extension of these techniques, we provide an implementation of the framework and embedding algorithms.

97 MATHEMATICS AND COMPUTING↗

Directive-Based, High-Level Programming and Optimizations for High-Performance Computing with FPGAs

Reconfigurable architectures like Field Programmable Gate Arrays (FPGAs) have been used for accelerating computations from several domains because of their unique combination of flexibility, performance, and power efficiency. However, FPGAs have not been widely used for high-performance computing, primarily because of their programming complexity and difficulties in optimizing performance. In this paper, we present a directive-based, high-level optimization framework for high-performance computing with FPGAs, built on top of an OpenACC-to-FPGA translation framework called OpenARC. We propose directive extensions and correspond- ing compile-time optimization techniques to enable the compiler to generate more efficient FPGA hardware configuration files. Empirical evaluation of the proposed framework on an Intel Stratix V with five OpenACC benchmarks from various application domains shows that FPGA-specific optimizations can lead to significant increases in performance across all tested applications. We also demonstrate that applying these high-level directive-based optimizations can allow OpenACC applications to perform similarly to lower-level OpenCL applications with hand-written FPGA-specific optimizations, and offer runtime and power performance benefits compared to CPUs and GPUs.

Lambert, Jacob↗

Just-in-Time Compilation and Link-Time Optimization for OpenMP Target Offloading

Following the mass adoption of external accelerators for high performance computing, the overall performance of many applications has become increasingly dependent on relatively small accelerated kernels. As static analysis is fundamentally limited by dynamic values and external definitions, standard ahead-of-time compilation is not always sufficient to achieve the best performance. Furthermore, many users looking to port an existing application to run on an external accelerator will not want to fundamentally restructure their programs. These and other problems can be addressed through both link-time optimization (LTO) and just-in-time (JIT) compilation, but until now had sparse and inconsistent support from the compiler. In this work, we present a new compilation method that enables device-side LTO as well as a transparent JIT compilation tool-chain for OpenMP target offloading. Our contributions include an entirely new device linking and embedding scheme to enable LTO as well as a novel JIT engine to efficiently optimize OpenMP offloading regions at run-time. We also introduce a persistent caching system to improve end-to-end runtime using the JIT engine and minimize kernel launching overheads. We measure the performance of our LTO and JIT implementation via several real-world scientific applications. With our optimizations we observe significant improvements through LTO on large applications as well as significant end-to-end execution time improvement using JIT.

Tian, Shilei↗

Berkeley Unified Parallel C (BUPC) Compiler

This program is a portable, open-source, compiler for the UPC language. It is based on the Open64 framework and has extensive support for optimizations. This compiler operates by translating UPC into ANSI/ISO C for compilation by a native compiler and linking with the UPC Runtime Library. This design eases portability to both shared- and distributed-memory parallel architectures. For proper operation it requires the "Berkeley Unified Parallel C (UPC) Runtime Library" and its dependencies.

Iancu, Costin↗

Grid Optimization (GO) Competition Platform

A software for a multi-challenge power-flow grid optimization competition was developed. The platform brings together high performance computing clusters, webservers, databases, competition datasets, schedulers, evaluation codes, and a multitude of language compilers and optimization solvers to host the competition. The original video announcing the competition, from former Secretary Perry, at: https://www.youtube.com/watch?v=hZwX3P9vS8M

Veeramany, Arun↗

Optimization with the OpenACC-to-FPGA framework on the Arria 10 and Stratix 10 FPGAs

The reconfigurable computing paradigm with field programmable gate arrays (FPGAs) has received renewed interest in the high-performance computing field due to FPGAs’ unique combination of performance and energy efficiency. However, difficulties in programming and optimizing FPGAs have prevented them from being widely accepted as general-purpose computing devices. In accelerator-based heterogeneous computing, portability across diverse heterogeneous devices is also an important issue, but the unique architectural features in FPGAs make this difficult to achieve. To address these issues, a directive-based, high-level FPGA programming and optimization framework was previously developed. In this work, developed optimizations were combined holistically using the directive-based approach to show that each individual benchmark requires a unique set of optimizations to maximize performance. We perform this exploration on Intel Arria 10 and Stratix 10 FPGAs. We also explored the relationships between performance, resource usages, and compilation times, and investigated implications for performance portability. Finally, we present an initial evaluation of a real-world proxy application, LULESH.

97 MATHEMATICS AND COMPUTING↗

Efficient, direct compilation of SU(N) operations into SNAP & Displacement gates

We present a function which connects the parameter of a previously published short sequence of selective number-dependent arbitrary phase (SNAP) and displacement gates acting on a qudit encoded into the Fock states of a superconducting cavity, $V_k(\alpha)=D(\alpha)R_\pi(k)D(-2\alpha)R_\pi(k)D(\alpha)$ to the angle of the Givens rotation $G(\theta)$ on levels $|k\rangle,|k+1\rangle$ that sequence approximates, namely $\alpha=\Phi(\theta) = \frac{\theta}{4\sqrt{k+1}}$. Previous publications left the determination of an appropriate $\alpha$ to numerical optimization at compile time. The map $\Phi$ gives us the ability to compile directly any $d$-dimensional unitary into a sequence of SNAP and displacement gates in $O(d^3)$ complex floating point operations with low constant prefactor, avoiding the need for numerical optimization. Numerical studies demonstrate that the infidelity of the generated gate sequence $V_k$ per Givens rotation $G$ scales as approximately $O(\theta^6)$. We find numerically that the error on compiled circuits can be made arbitrarily small by breaking each rotation into $m$$\theta/m$ rotations, with the full $d\times d$ unitary infidelity scaling as approximately $O(m^{-4})$. This represents a significant reduction in the computational effort to compile qudit unitaries either to SNAP and displacement gates or to generate them via direct low-level pulse optimization via optimal control.

Job, Joshua↗

Understanding the Design Space of Sparse/Dense Multiphase Dataflows for Mapping Graph Neural Networks on Spatial Accelerators

Graph Neural Networks (GNNs) have garnered a lot of recent interest because of their success in learning representations from graph-structured data across several critical applications in cloud and HPC. Owing to their unique compute and memory characteristics that come from an interplay between dense and sparse phases of computations, the emergence of reconfigurable dataflow (aka spatial) accelerators offers promise for acceleration by mapping optimized dataflows (i.e., computation order and parallelism) for both phases. The goal of this work is to characterize and understand the design-space of dataflow choices for running GNNs on spatial accelerators in order for the compilers to optimize the dataflow based on the workload. Specifically, we propose a taxonomy to describe all possible choices for mapping the dense and sparse phases of GNNs spatially and temporally over a spatial accelerator, capturing both the intra-phase dataflow and the inter-phase (pipelined) dataflow. Using this taxonomy, we do deep-dives into the cost and benefits of several dataflows and perform case studies on implications of hardware parameters for dataflows and value of flexibility to support pipelined execution.

97 MATHEMATICS AND COMPUTING↗

Cache Locality Optimization for Recursive Programs

We present an approach to optimize the cache locality for recursive programs by dynamically splicing--recursively interleaving--the execution of distinct function invocations. By utilizing data effect annotations, we identify concurrency and data reuse opportunities across function invocations and interleave them to reduce reuse distance. We present algorithms that efficiently track effects in recursive programs, detect interference and dependencies, and interleave execution of function invocations using user-level (non-kernel) lightweight threads. To enable multi-core execution, a program is parallelized using a nested fork/join programming model. Our cache optimization strategy is designed to work in the context of a random work stealing scheduler. We present an implementation using the MIT Cilk framework that demonstrates significant improvements in sequential and parallel performance, competitive with a state-of-the-art compile-time optimizer for loop programs and a domain- specific optimizer for stencil programs.

Lifflander, Jonathan↗

Reductive Analysis with Compiler-Guided Large Language Models for Input-Centric Code Optimizations

Input-centric program optimization aims to optimize code by considering the relations between program inputs and program behaviors. Despite its promise, a long-standing barrier for its adoption is the difficulty of automatically identifying critical features of complex inputs. This paper introduces a novel technique, reductive analysis through compiler-guided Large Language Models (LLMs), to solve the problem through a synergy between compilers and LLMs. It uses a reductive approach to overcome the scalability and other limitations of LLMs in program code analysis. The solution, for the first time, automates the identification of critical input features without heavy instrumentation or profiling, cutting the time needed for input identification by 44× (or 450× for local LLMs), reduced from 9.6 hours to 13 minutes (with remote LLMs) or 77 seconds (with local LLMs) on average, making input characterization possible to be integrated into the workflow of program compilations. Optimizations on those identified input features show similar or even better results than those identified by previous profiling-based methods, leading to optimizations that yield 92.6% accuracy in selecting the appropriate adaptive OpenMP parallelization decisions, and 20-30% performance improvement of serverless computing while reducing resource usage by 50-60%.

Input-Centric Optimization↗

SQUARE: Strategic Quantum Ancilla Reuse for Modular Quantum Programs via Cost-Effective Uncomputation

Compiling high-level quantum programs to machines that are size constrained (i.e. limited number of quantum bits) and time constrained (i.e. limited number of quantum operations) is challenging. In this paper, we present SQUARE (Strategic QUantum Ancilla REuse), a compilation infrastructure that tackles allocation and reclamation of scratch qubits (called ancilla) in modular quantum programs. At its core, SQUARE strategically performs uncomputation to create opportunities for qubit reuse. Current Noisy Intermediate-Scale Quantum (NISQ) computers and forward-looking Fault-Tolerant (FT) quantum computers have fundamentally different constraints such as data locality, instruction parallelism, and communication overhead. Our heuristic-based ancilla-reuse algorithm balances these considerations and fits computations into resource-constrained NISQ or FT quantum machines, throttling parallelism when necessary. To precisely capture the workload of a program, we propose an improved metric, the "active quantum volume," and use this metric to evaluate the effectiveness of our algorithm. Furthermore, our results show that SQUARE improves the average success rate of NISQ applications by 1.47X. Surprisingly, the additional gates for uncomputation create ancilla with better locality, and result in substantially fewer swap gates and less gate noise overall. SQUARE also achieves an average reduction of 1.5X (and up to 9.6X) in active quantum volume for FT machines.

compiler optimization↗

Towards Achieving Performance Portability Using Directives for Accelerators

In this paper we explore the performance portability of directives provided by OpenMP 4 and OpenACC to program various types of node architectures with attached accelerators, both self-hosted multicore and offload multicore/GPU. Our goal is to examine how successful OpenACC and the newer offload features of OpenMP 4.5 are for moving codes between architectures, how much tuning might be required and what lessons we can learn from this experience. To do this, we use examples of algorithms with varying computational intensities for our evaluation, as both compute and data access efficiency are important considerations for overall application performance. We implement these kernels using various methods provided by newer OpenACC and OpenMP implementations, and we evaluate their performance on various platforms including both X86_64 with attached NVIDIA GPUs, self-hosted Intel Xeon Phi KNL, as well as an X86_64 host system with Intel Xeon Phi coprocessors. In this paper, we explain what factors affected the performance portability such as how to pick the right programming model, its programming style, its availability on different platforms, and how well compilers can optimize and target to multiple platforms.

97 MATHEMATICS AND COMPUTING↗

MO-DE-BRA-05: EUTEMPE-RX: Combining E-Learning and Face-To-Face Training to Build Expert Knowledge, Skills and Competences for Medical Physicists in Diagnostic and Interventional Radiology

Purpose: In 2013, the EURATOM authorities of the European Commission decided to support the Horizon2020 project submission ‘EUTEMPE-RX’ that aimed for a new set of course modules to train medical physicists in diagnostic and interventional radiology to expert level with small group deep learning. Each module would consist of 2 phases: an e-learning and a face-to-face phase, each phase requiring typically 40h of participant time. Methods: The European Federation (EFOMP) and 13 European partners, all of them selected for their excellent scientific and/or educational skills, led the 12 course modules. A quality manual ensured the quality of course content and organization. Educational workshops familiarized the teachers with e-learning techniques and methods for assessment. Content was set in accordance with the EC document RP174 that lists learning outcomes in terms of knowledge, skills and competences (KSCs) for different specialties and levels of medical physics. Surveys for stake holder satisfaction were prepared. Results: Today the course modules are being realized. The modules cover most of the KSCs in RP174 document. Teachers have challenged the participants with unique tasks: case studies in medical physics leadership, Monte Carlo simulation of a complete x-ray imaging chain, development of a task specific QA protocol, compilation of optimization plans, simulation tasks with anthropomorphic breast models, etc. Participants undertook practical sessions in modern hospitals and visited a synchrotron facility, a calibration lab, screening organizations, etc. Feedback form quality surveys was very positive and constructive. A sustainability plan has been worked out. Conclusion: The modules have enabled the participants to develop their KSCs and cope with challenges in medical physics. The sustainability plan will be implemented to continue the unique combined e-learning and face to face training at high level training in diagnostic and interventional radiology also beyond Europe. The EUTEMPE-RX project is funded by the Horizon2020 - EURATOM program of the European Commission.

60 APPLIED LIFE SCIENCES↗

Application Experiences on a GPU-Accelerated Arm-based HPC Testbed

This paper assesses and reports the experience of ten teams working to port, validate, and benchmark several High Performance Computing applications on a novel GPU-accelerated Arm testbed system. The testbed consists of eight NVIDIA Arm HPC Developer Kit systems, each one equipped with a server-class Arm CPU from Ampere Computing and two data center GPUs from NVIDIA Corp. The systems are connected together using InfiniBand interconnect. The selected applications and mini-apps are written using several programming languages and use multiple accelerator-based programming models for GPUs such as CUDA, OpenACC, and OpenMP offloading. Working on application porting requires a robust and easy-to-access programming environment, including a variety of compilers and optimized scientific libraries. The goal of this work is to evaluate platform readiness and assess the effort required from developers to deploy well-established scientific workloads on current and future generation Arm-based GPU-accelerated HPC systems. The reported case studies demonstrate that the current level of maturity and diversity of software and tools is already adequate for large-scale production deployments.

Elwasif, Wael↗