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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Magnetic flux imaging in a 3D superconductor integrated circuit

We report on imaging magnetic flux distributions in a multilayered superconductor integrated circuit which emerge during magnetization and after field cooling of the circuit in the DC magnetic field. The obtained complicated field maps expose the flux propagation across the patterned superconducting ground planes sandwiching layers with Josephson junction-based logic cells, fine wire grid around the functional units, and multiple superconducting fill structures located in different inner layers. The observed intricate flux distributions are explained by specific patterns of Meissner screening currents and superconducting critical currents in different mutually interacting parts of the integrated circuit. Our results provide important insights into possible ways of improving the protection of superconductor integrated circuits from magnetic fields and their resilience against flux trapping.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

A circuit-generated quantum subspace algorithm for the variational quantum eigensolver

Recent research has shown that wavefunction evolution in real and imaginary time can generate quantum subspaces with significant utility for obtaining accurate ground state energies. Inspired by these methods, we propose combining quantum subspace techniques with the variational quantum eigensolver (VQE). In our approach, the parameterized quantum circuit is divided into a series of smaller subcircuits. The sequential application of these subcircuits to an initial state generates a set of wavefunctions that we use as a quantum subspace to obtain high-accuracy groundstate energies. We call this technique the circuit subspace variational quantum eigensolver (CSVQE) algorithm. By benchmarking CSVQE on a range of quantum chemistry problems, we show that it can achieve significant error reduction in the best case compared to conventional VQE, particularly for poorly optimized circuits, greatly improving convergence rates. Furthermore, we demonstrate that when applied to circuits trapped at local minima, CSVQE can produce energies close to the global minimum of the energy landscape, making it a potentially powerful tool for diagnosing local minima.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2024

Learning linear optical circuits with coherent states

We analyze the energy and training data requirements for supervised learning of an M-mode linear optical circuit by minimizing an empirical risk defined solely from the action of the circuit on coherent states. When the linear optical circuit acts non-trivially only on k < M unknown modes (i.e. a linear optical k-junta), we provide an energy-efficient, adaptive algorithm that identifies the junta set and learns the circuit. We compare two schemes for allocating a total energy, E, to the learning algorithm. In the first scheme, each of the T random training coherent states has energy E/T. In the second scheme, a single random MT-mode coherent state with energy E is partitioned into T training coherent states. The latter scheme exhibits a polynomial advantage in training data size sufficient for convergence of the empirical risk to the full risk due to concentration of measure on the $(2MT-1)$-sphere. Specifically, generalization bounds for both schemes are proven, which indicate that for ε-approximation of the full risk by the empirical risk with high probability, $O(E^{2/3}M^{2/3}/\epsilon^{2/3})$ training states are sufficient for the first scheme and $O(E^{1/3}M^{1/3}/\epsilon^{2/3})$ training states are sufficient for the second scheme.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2025

Logical error rates for the surface code under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions

With fault-tolerant quantum computing (FTQC) on the horizon, it is critical to understand sources of logical errors in plausible hardware implementations of quantum error-correcting codes. Detailed error modeling of computational instructions on particular FTQC architectures will enable the better prediction of error propagation in FT-encoded quantum circuits while revealing where greater attention is needed in hardware design. In this work, we consider logical error rates for the surface code implemented on a hypothetical grid-based trapped-ion quantum charge-coupled device architecture. Specifically, we construct logical channels for the idling surface code and examine its diamond error under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions. We include the coherent dephasing noise that is known to accumulate during physical qubit idling and transport in these systems, determining idling and transport durations using the time-resolved output of an open-source trapped-ion surface code compiler. To estimate expectation values of logical Pauli observables following hardware circuits containing non-Clifford sources of noise, we utilize a Monte Carlo technique to sample from an underlying quasiprobability distribution of Clifford circuits that we independently simulate in a phase-sensitive fashion. We verify error suppression up to code distance 𝑑 = 11 at coherent dephasing rates near and below those of current-generation trapped-ion quantum computers and find that logical error rates align with those of analogous fully stochastic simulations in this regime. Exploring higher dephasing rates at 𝑑 = 3−5, we find evidence for growing coherent rotations about all three logical Pauli axes, increased diagonal logical error process matrix elements relative to those of stochastic simulations, and a reduced dephasing rate threshold. Overall, our work paves a way toward realistic hardware emulation of small fault-tolerant quantum processes, e.g., members of an FTQC instruction set.

Quantum benchmarking↗
DOE OSTI2024

Acceptor-Induced Bulk Dielectric Loss in Superconducting Circuits on Silicon

The performance of superconducting quantum circuits is primarily limited by dielectric loss due to interactions with two-level systems (TLSs). State-of-the-art circuits with engineered material interfaces are approaching a limit where dielectric loss from bulk substrates plays an important role. However, a microscopic understanding of dielectric loss in crystalline substrates is still lacking. In this work, we show that boron acceptors in silicon constitute a TLS bath that leads to an energy dissipation channel for superconducting circuits. We discuss how the electronic structure of boron acceptors leads to an effective TLS response in silicon. We sweep the boron concentration in silicon and demonstrate the bulk dielectric loss limit from boron acceptors. We show that boron-induced dielectric loss can be reduced in a magnetic field due to the spin-orbit structure of boron. This work provides the first detailed microscopic description of a TLS bath for superconducting circuits and demonstrates the need for ultrahigh-purity substrates for next-generation superconducting quantum processors.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

Grid Forming Inverter With Increased Short-Circuit Contribution to Address Inverter-Based Microgrid Protection Challenges

Substantial differences in fault levels between grid-tied and islanded modes is one of the primary challenges of microgrid protection. During grid-tied mode, the bulk grid provides significant short-circuit, while during islanded operation the short-circuit magnitude is small due to inverter-based resources limiting their current output close to nominal ratings. Consequently, conventional distribution protection strategies based on overcurrent cannot reliably protect microgrids when operating in islanded mode. Fuses and circuit breakers are particularly affected because of their inverse characteristics. Presently, the absence of affordable solutions for protecting microgrids in islanded mode leads to microgrids shutting down during electrical faults. The contribution of this article is two-fold. The first innovation proposes specific hardware modifications to grid-forming inverters to increase their short-circuit current during electrical faults. The second innovation introduces a novel control strategy designed to preserve control stability margins even when the grid-filter saturates, ensuring sinusoidal output currents under normal and fault conditions. Through experimental results, the inverter with the proposed modifications can provide more than three-times its nominal current during electrical faults. For the prototype testbed, this was sufficient to enable the use of traditional legacy overcurrent protection, achieving the fuse-to-relay and relay-to-relay minimum coordination time for the line-to-ground, line-to-line to ground, and three-phase electrical faults.

42 ENGINEERING↗
DOE OSTI2024

Impact of K-factor on Short Circuit Program Convergence for Inverter-Based Resources during Faults

Classical short-circuit programs that linearize the power network are no longer applicable for inverter based resources (IBRs), necessitating an iterative approach. Phasor domain programs can model the IBRs using an iterative approach considering nonlinear fault responses. In phasor domain models, the IBR can be modeled as a voltage controlled current source (VCCS) in tabular form with positive, negative, and zero sequence information for balanced and unbalance short-circuit faults. In the VCCS modeling of the IBR, positive and negative incremental reactive current, also known as the k-factor, plays an important role in short circuit program convergence. In this work, a few approaches: conventional VCCS modeling with a k-factor of 2, conventional VCCS modeling with a k-factor of 2 with modified pre-fault voltages, VCCS characteristics based on the power flow solution with a k-factor of 2, and VCCS characteristics based on the power flow solution with a k-factor of 1 are investigated for short circuit program convergence under higher IBR penetration. The IEEE 39 bus New England Test System is taken as the test system, and simulations are carried out in PSS®CAPE 15.0.26 simulation software. Simulation results demonstrate that IBR penetration is higher for the VCCS model, which corresponds to the power flow solution with k-factor 1, compared to other approaches.

42 ENGINEERING↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
DOE OSTI2025

Any Clifford+T circuit can be controlled with constant T-depth overhead

Since an n-qubit circuit consisting of CNOT gates can have up to $Ω(n^2/\log{n})$ CNOT gates, it is natural to expect that $Ω(n^2/\log{n})$ Toffoli gates are needed to apply a controlled version of such a circuit. We show that the Toffoli count can be reduced to at most n. The Toffoli depth can also be reduced to O(1), at the cost of 2n Toffoli gates, even without using any ancilla or measurement. In fact, using a measurement-based uncomputation, the Toffoli depth can be further reduced to 1. From this, we give two corollaries: any controlled Clifford circuit can be implemented with O(1) T-depth, and any Clifford+T circuit with T-depth D can be controlled with T-depth O(D), even without ancillas. As an application, we show how to catalyze a rotation by any angle up to precision $ε$ in T-depth exactly 1 using a universal $\lceil\log_2(8/ε)\rceil$-qubit catalyst state.

FOS: Physical sciences↗
DOE OSTI2025

Cost of emulating a small quantum annealing problem in the circuit model

Demonstrations of quantum advantage for certain sampling problems have generated considerable excitement for quantum computing and have further spurred the development of circuit-model quantum computers, which represent quantum programs as a sequence of quantum gates acting on a finite number of qubits. Amongst this excitement, analog quantum computation has become less prominent, with the expectation that circuit-model quantum computers will eventually be sufficient for emulating analog quantum computation and thus rendering analog quantum computation obsolete. In this work we explore the basic requirements for emulating a specific analog quantum computation in the circuit model: the preparation of a biased superposition of degenerate ground states of an Ising Hamiltonian using an adiabatic evolution. We show that the overhead of emulation is substantial even for this simple problem. This supports using analog quantum computation for solving time-dependent Hamiltonian dynamics in the short term and midterm, assuming analog errors can be made low enough and coherence times long enough to solve problems of practical interest.

Quantum algorithms & computation↗
DOE OSTI2025

Harnessing ionic complexity: A modeling approach for hierarchical ionic circuit design

Since the 1950s, soft ionic devices have evolved from individual components to an expanding library of sensors, actuators, signal transmitters, and processors. However, integrating these components into complex, multifunctional systems remains challenging due to the nonintuitive and nonlinear interactions between ionic elements. In this work, we address these fundamental challenges by developing a lumped element model that enables interrogation of the physics that governs ionic circuits, as well as rapid design and optimization. Our model captures features specific to ionic charge carriers, while preserving the hierarchical design flexibility and computational efficiency of traditional circuit modeling. We demonstrate that our model can not only fit individual device behavior but also accurately predict the behavior of larger circuits formed by combining those devices. Additionally, we show how our tool utilizes the intrinsic nonlinearities of ionic systems to enable extended functionality, revealing how factors such as ion enrichment, ion leakage, and polymer charge density influence performance. Lastly, we present a fully ionic power supply, sensor, control system, and actuator for a soft robot that adapts its motion in response to environmental salt, illustrating the tool’s potential to accelerate advancements in chemical sensing, biointerfacing, biomimetic systems, and adaptive materials.

42 ENGINEERING↗
DOE OSTI2024

Strong Zero Modes in Integrable Quantum Circuits

It is a classic result that certain interacting integrable spin chains host robust edge modes known as strong zero modes (SZMs). In this Letter, we extend this result to the Floquet setting of local quantum circuits, focusing on a prototypical model providing an integrable Trotterization for the evolution of the XXZ Heisenberg spin chain. By exploiting the algebraic structures of integrability, we show that an exact SZM operator can be constructed for these integrable quantum circuits in certain regions of parameter space. Our construction, which recovers a well-known result by Paul Fendley in the continuous-time limit, relies on a set of commuting transfer matrices known from integrability, and allows us to easily prove important properties of the SZM, including normalizabilty. Our approach is different from previous methods and could be of independent interest even in the Hamiltonian setting. Furthermore, our predictions, which are corroborated by numerical simulations of infinite-temperature autocorrelation functions, are potentially interesting for implementations of the XXZ quantum circuit on available quantum platforms.

1-dimensional spin chains↗
DOE OSTI2024

Approximate 𝑡-Designs in Generic Circuit Architectures

Unitary 𝑡-designs are distributions on the unitary group whose first 𝑡 moments appear maximally random. Previous work has established several upper bounds on the depths at which certain specific random quantum circuit ensembles approximate 𝑡-designs. Here we show that these bounds can be extended to any fixed architecture of Haar-random two-site gates. This is accomplished by relating the spectral gaps of such architectures to those of one-dimensional brickwork architectures. Our bound depends on the details of the architecture only via the typical number of layers needed for a block of the circuit to form a connected graph over the sites. When this quantity is bounded, the circuit forms an approximate 𝑡-design in at most linear depth. We give numerical evidence for a stronger bound that depends only on the number of connected blocks into which the architecture can be divided. We also give an implicit bound for nondeterministic architectures in terms of properties of the corresponding distribution over fixed architectures.

information scrambling↗
DOE OSTI2024

Equivalent-Circuit Models of Grid-Forming IBRs for Electromagnetic-Transient Simulations

We derive equivalent-circuit models of control- and physical-layer subsystems of grid-forming (GFM) inverter-based resources (IBRs) for electromagnetic-transient (EMT) simulations. Three different primary controllers are considered: Droop, Virtual Synchronous Machine (VSM), and dispatchable Virtual Oscillator Control (dVOC). In addition, the models include cascaded voltage- and current-control loops, and LCL output filters. Simulations for a single-inverter setup and for a network of five inverters in a modified IEEE 14-bus topology are presented. The equivalent-circuit models simulated with analog electronic circuit-simulator software (in our case, LTspice) offer the same accuracy, and with no explicit tuning of the solver, lower computational burden compared to block-diagram-based implementations in commercial off-the-shelf EMT software (in our case, MATLAB-Simulink).

electromagnetic transient simulation↗
DOE OSTI2025

Large-signal Stability Analysis of Grid-forming Inverters with Equivalent-circuit Models

Here, this paper proposes an energy function-based direct method for large-signal stability assessment of grid-forming (GFM) inverters leveraging an equivalent-circuit representation of all involved control- and physical-layer dynamics. Three different primary controls, a standard inner-current outer-voltage cascaded-control architecture, output LCL filter, and reference-current saturation limiting are featured in the modeling and analysis framework. A composite energy function for the GFM inverter is obtained by summing up individual energy contributions gleaned from the circuit representation. The approach can readily be generalized to different primary controls, output-filter arrangements, and current limiters since it is based on a circuit-theoretic foundation. Numerical simulations validate the efficacy of the approach in estimating the critical clearing time following a large-signal disturbance.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2026

Inverter-Based Power Systems From an Electric Circuit Perspective

This presentation reports a twin circuit theory that enables us to interpret power system dynamics from a electric circuit perspective. Our proposed twin circuit theory can roughly prove the dissipating energy flow (DEF) method, and shows the positive impacts of well-designed grid-forming (GFM) inverters on power systems stability.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2022

Variational Quantum Circuits to Prepare Low Energy Symmetry States

We explore how to build quantum circuits that compute the lowest energy state corresponding to a given Hamiltonian within a symmetry subspace by explicitly encoding it into the circuit. We create an explicit unitary and a variationally trained unitary that maps any vector output by ansatz A(α → ) from a defined subspace to a vector in the symmetry space. The parameters are trained varitionally to minimize the energy, thus keeping the output within the labelled symmetry value. The method was tested for a spin XXZ Hamiltonian using rotation and reflection symmetry and H 2 Hamiltonian within S z = 0 subspace using S 2 symmetry. We have found the variationally trained unitary gives good results with very low depth circuits and can thus be used to prepare symmetry states within near term quantum computers.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Equivalent-Circuit Models of Grid-Forming IBRs for Electromagnetic-Transient Simulations: Preprint

We derive equivalent-circuit models of control- and physical-layer subsystems of grid-forming (GFM) inverter-based resources (IBRs) for electromagnetic-transient (EMT) simulations. Three different primary controllers are considered: droop, virtual synchronous machine (VSM), and dispatchable virtual oscillator control (dVOC). In addition, the models include cascaded voltage- and current-control loops, and LCL output filters. Simulations for a single-inverter setup and for a network of five inverters in a modified IEEE 14-bus topology are presented. The equivalent-circuit models simulated with analog electronic circuit-simulator software (in our case, LTspice) offer the same accuracy with up to 150x lower computational burden compared to block-diagram-based implementations in commercial off-the-shelf EMT software (in our case, MATLAB-Simulink).

circuit-equivalent model↗