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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Cascaded VLSI Chips Help Neural Network To Learn

Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

Duong, Tuan A.↗
NASA NTRS1993

The role of simulation in the design of a neural network chip

An iterative, simulation-based design procedure for a neural network chip is introduced. For this design procedure, the goal is to produce a chip layout for a neural network in which the weights are determined by transistor gate width-to-length ratios. In a given iteration, the current layout is simulated using the circuit simulator SPICE, and layout adjustments are made based on conventional gradient-decent methods. After the iteration converges, the chip is fabricated. Monte Carlo analysis is used to predict the effect of statistical fabrication process variations on the overall performance of the neural network chip.

Desai, Utpal↗
NASA NTRS1996

Chip-on-Board Technology 1996 Year-end Report (Design, Manufacturing, and Reliability Study)

The major impetus for flight qualifying Chip-On-Board (COB) packaging technology is the shift in emphasis for space missions to smaller, better, and cheaper spacecraft and satellites resulting from the NASA New Millenium initiative and similar requirements in DoD-sponsored programs. The most important benefit that can potentially be derived from miniaturizing spacecraft and satellites is the significant cost saving realizable if a smaller launch vehicle may be employed. Besides the program cost saving, there are several other advantages to building COB-based space hardware. First, once a well-controlled process is established, COB can be low cost compared to standard Multi-Chip Module (MCM) technology. This cost competitiveness is regarded as a result of the generally greater availability and lower cost of Known Good Die (KGD). Coupled with the elimination of the first level of packaging (chip package), compact, high-density circuit boards can be realized with Printed Wiring Boards (PWB) that can now be made with ever-decreasing feature size in line width and via hole. Since the COB packaging technique in this study is based mainly on populating bare dice on a suitable multi-layer laminate substrate which is not hermetically sealed, die coating for protection from the environment is required. In recent years, significant improvements have been made in die coating materials which further enhance the appeal of COB. Hysol epoxies, silicone, parylene and silicon nitride are desirable because of their compatible Thermal Coefficient of Expansion (TCE) and good moisture resistant capability. These die coating materials have all been used in the space and other industries with varying degrees of success. COB technology, specifically siliconnitride coated hardware, has been flown by Lockheed on the Polar satellite. In addition, DARPA has invested a substantial amount of resources on MCM and COB-related activities recently. With COB on the verge of becoming a dominant player in DoD programs, DARPA is increasing its support of the availability of KGDs which will help decrease their cost. Aside from the various major developments and trends in the space and defense industries that are favorable to the acceptance and widespread use of'COB packaging technology, implementing COB can be appealing in other aspects. Since the interconnection interface is usually the weak link in a system, the overall circuit or system reliability may actually be improved because of the elimination of a level of interconnect/packaging at the chip. With COB, mixing packaging technologies is possible. Because some devices are only available in commercial plastic packages, populating a multi-layer laminate substrate with both bare dice and plastic-package parts is inevitable. Another attractive feature of COB is that re-workability is possible if die coating is applied only on the die top. This method allows local replacement of individual dice that were found to be defective instead of replacing an entire board. In terms of thermal management, unpackaged devices offer a shorter thermal resistance path than their packaged counterparts thereby improving thermal sinking and heat removal from the parts.

Le, Binh Q.↗
NASA NTRS2003

Single chip camera active pixel sensor

A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

Shaw, Timothy↗
NASA NTRS2008

Update on Development of SiC Multi-Chip Power Modules

Progress has been made in a continuing effort to develop multi-chip power modules (SiC MCPMs). This effort at an earlier stage was reported in 'SiC Multi-Chip Power Modules as Power-System Building Blocks' (LEW-18008-1), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 28. The following recapitulation of information from the cited prior article is prerequisite to a meaningful summary of the progress made since then: 1) SiC MCPMs are, more specifically, electronic power-supply modules containing multiple silicon carbide power integrated-circuit chips and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking; 2) The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules; and, 3) In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications. Because identical SiC MCPM building blocks could be utilized in such a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. This concludes the information from the cited prior article. The main activity since the previously reported stage of development was the design, fabrication, and testing a 120- VDC-to-28-VDC modular power-converter system composed of eight SiC MCPMs in a 4 (parallel)-by-2 (series) matrix configuration, with normally-off controllable power switches. The SiC MCPM power modules include closed-loop control subsystems and are capable of operating at high power density or high temperature. The system was tested under various configurations, load conditions, load-transient conditions, and failure-recovery conditions. Planned future work includes refinement of the demonstrated modular system concept and development of a new converter hardware topology that would enable sharing of currents without the need for communication among modules. Toward these ends, it is also planned to develop a new converter control algorithm that would provide for improved sharing of current and power under all conditions, and to implement advanced packaging concepts that would enable operation at higher power density.

Lostetter, Alexander↗
NASA NTRS2010

System on a Chip (SoC) Overview

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

LaBel, Kenneth A.↗
NASA NTRS2014

AE (Acoustic Emission) for Flip-Chip CGA/FCBGA Defect Detection

C-mode scanning acoustic microscopy (C-SAM) is a nondestructive inspection technique that uses ultrasound to show the internal feature of a specimen. A very high or ultra-high-frequency ultrasound passes through a specimen to produce a visible acoustic microimage (AMI) of its inner features. As ultrasound travels into a specimen, the wave is absorbed, scattered or reflected. The response is highly sensitive to the elastic properties of the materials and is especially sensitive to air gaps. This specific characteristic makes AMI the preferred method for finding "air gaps" such as delamination, cracks, voids, and porosity. C-SAM analysis, which is a type of AMI, was widely used in the past for evaluation of plastic microelectronic circuits, especially for detecting delamination of direct die bonding. With the introduction of the flip-chip die attachment in a package; its use has been expanded to nondestructive characterization of the flip-chip solder bumps and underfill. Figure 1.1 compares visual and C-SAM inspection approaches for defect detection, especially for solder joint interconnections and hidden defects. C-SAM is specifically useful for package features like internal cracks and delamination. C-SAM not only allows for the visualization of the interior features, it has the ability to produce images on layer-by-layer basis. Visual inspection; however, is only superior to C-SAM for the exposed features including solder dewetting, microcracks, and contamination. Ideally, a combination of various inspection techniques - visual, optical and SEM microscopy, C-SAM, and X-ray - need to be performed in order to assure quality at part, package, and system levels. This reports presents evaluations performed on various advanced packages/assemblies, especially the flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. Both external and internal equipment was used for evaluation. The outside facility provided images of the key features that could be detected using the most advanced C-SAM equipment with a skilled operator. Investigation continued using in-house equipment with its limitations. For comparison, representative X-rays of the assemblies were also gathered to show key defect detection features of these non-destructive techniques. Key images gathered and compared are: Compared the images of 2D X-ray and C-SAM for a plastic LGA assembly showing features that could be detected by either NDE technique. For this specific case, X-ray was a clear winner. Evaluated flip-chip CGA and FCBGA assemblies with and without heat sink by C-SAM. Only the FCCGA package that had no heat sink could be fully analyzed for underfill and bump quality. Cross-sectional microscopy did not revealed peripheral delamination features detected by C-SAM. Analyzed a number of fine pitch PBGA assemblies by C-SAM. Even though the internal features of the package assemblies could be detected, C-SAM was unable to detect solder joint failure at either the package or board level. Twenty times touch ups by solder iron with 700degF tip temperature, each with about 5 second duration, did not induce defects to be detected by C-SAM images. Other techniques need to be considered to induce known defects for characterization. Given NASA's emphasis on the use of microelectronic packages and assemblies and quality assurance on workmanship defect detection, understanding key features of various inspection systems that detect defects in the early stages of package and assembly is critical to developing approaches that will minimize future failures. Additional specific, tailored non-destructive inspection approaches could enable low-risk insertion of these advanced electronic packages having hidden and fine features.

Ghaffarian, Reza↗
NASA NTRS2015

On-Chip Power-Combining for High-Power Schottky Diode Based Frequency Multipliers

A novel MMIC on-chip power-combined frequency multiplier device and a method of fabricating the same, comprising two or more multiplying structures integrated on a single chip, wherein each of the integrated multiplying structures are electrically identical and each of the multiplying structures include one input antenna (E-probe) for receiving an input signal in the millimeter-wave, submillimeter-wave or terahertz frequency range inputted on the chip, a stripline based input matching network electrically connecting the input antennas to two or more Schottky diodes in a balanced configuration, two or more Schottky diodes that are used as nonlinear semiconductor devices to generate harmonics out of the input signal and produce the multiplied output signal, stripline based output matching networks for transmitting the output signal from the Schottky diodes to an output antenna, and an output antenna (E-probe) for transmitting the output signal off the chip into the output waveguide transmission line.

Siles Perez, Jose Vicente↗
NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗
NASA NTRS2020

Organic flip chip reliability study for space applications

The current state-of-the-art flip chip packages for space applications are the class-Y non-hermetic ceramic packages, whereas for commercial applications, organic packages have been the mainstream technology for about two decades. The high reliability of the class-Y parts suggests that the hermeticity is not critical for the reliability of flip chip devices and that organic flip chip packages could be reliable enough for space applications. The current report summarizes the result of collaboration between JPL and Cobham semiconductor space solutions to study the reliability of the organic flip chip packages.

Measmer, Rich↗
DOE OSTI2025

Initial assessment of second generation of large-area picosecond photodetectors with multi-channel systems-on-a-chip readout

Here, we first briefly describe the history and motivation behind Cherenkov and scintillation light detection. We then discuss the instrumentation needed to detect these photons as it applies to both photodetectors and readout electronics. One of the motivations is future large neutrino detectors that could, in principle, differentiate between Cherenkov and scintillation light if using novel water-based scintillators. In this paper, we present the first measurements utilizing the second generation of Large Area Picosecond Photodetectors (LAPPDs) in conjunction with commercial system-on-a-chip readouts from Nalu Scientific—in particular, the High Density System on Chip (HDSoC) and Advanced ASoC Rapid Digitizer, Variable Adaptive Readout Chip (AARDVARC) platforms. These state-of-the-art full-waveform digitizers feature sampling rates on the order of 1 and 10 samples per nanosecond, respectively. Using a picosecond laser, we measured the timing jitter between a pair of LAPPD channels, demonstrating the potential of this setup for precise timing applications.

Li, V. A. [Lawrence Livermore National Laboratory ↗
DOE OSTI2025

SALSA: a new versatile readout chip for MPGD detectors

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other usages of MPGD detectors like TPC or photon detectors. It integrates a frontend block and an ADC for each of the 64 channels, associated to a configurable DSP processor meant to correct data and reduce the raw data flux to limit the output bandwidth. It will be compatible with the continuous readout foreseen for the EPIC DAQ, but will also work in a triggered environment. Several prototypes are already produced in order to qualify the different blocks of the chip, in particular the frontend, the ADC and the clock generation. The next 32-channel prototype is currently under development and is planed to be produced in 2025. In conclusion, the final prototype will be produced and tested from 2026 for a production of the SALSA chip at the horizon of 2027.

Data processing↗
DOE OSTI2026

Low power on-chip data transmission for wafer-scale monolithic active pixel sensors

Here, this paper details the implementation of the digital pulse shaping subsystem within the Backbone Transmission Line Encoding (BTLE) driver, a low-power, long-distance on-chip data transmission solution designed in a 65 nm CMOS process. Digital pulse shaping is critical for minimizing inter-symbol interference (ISI) caused by bandwidth limitations of on-chip interconnects, especially in wafer-scale monolithic active pixel sensors (MAPS). A duobinary encoder coupled with a parallelized polyphase finite impulse response (FIR) filter is used for efficient shaping of the transmitted signal spectrum. This reconfigurable architecture achieves reliable 160 Mb/s data transfer over a 10 cm on-chip link, as validated by simulations demonstrating low power consumption (FoM 37.3 fJ/bit/mm of transmission line length) and effective ISI mitigation.

47 OTHER INSTRUMENTATION↗
DOE OSTI2026

A Unidirectional Two-Compartment Neuron Circuit with On-chip STDP learning

Most neuromorphic chips implement the single-compartment point neuron model where synapse circuits connect directly to a leaky integrate and fire (LIF) soma circuit. However, when using a biologically plausible soma circuit (e.g., Hodgkin-Huxley neuron model), an interface circuitry, such as a current conveyor circuit, is needed to transmit synaptic current to the soma circuit. This is especially true for ultra-low power neuron circuits, where membrane capacitance is on the order of 20 fF. This need for an interface circuit arises because the parasitic capacitance and leakage current caused by fabrication mismatch and second-order effects of the output transistors in the synapse circuits can disturb the spiking dynamics of the soma circuit if connected without an interface. Using an interface circuit to isolate the soma’s membrane capacitor from synapses resolves this issue. We propose to use a unidirectional resistor (a transconductance circuit) to connect the synapse and soma circuits instead of conventional current conveyor circuits. Using a biologically plausible spike pattern detection model, we show that the on-chip spike-timing-dependent plasticity (STDP) learning performance of the proposed unidirectional two-compartment neuron circuit is similar to a single-compartment circuit (with a current conveyor as an interface) and additionally, it is more power-efficient and biologically plausible. The chip is fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm technology node and comprises a single neuron circuit.

Gautam, Ashish [ORNL]↗
DOE OSTI2024

High power chip-scale laser

The lack of high-power integrated lasers has been limiting silicon photonics. Despite much progress in chip-scale laser integration, power output remains below levels required for key applications due to low energy efficiency at high pumping currents. Here we break this power limitation by coupling a broad-area multimode gain chip to a silicon-nitride ring resonator and single-mode filter. The resulting optical feedback causes the multimode-gain chip to concentrate its power into a single highly coherent mode. Our device produces more than 150 mW of power and 400 kHz linewidth. We achieve these metrics while maintaining a small footprint of 3 mm 2 .

Antman, Yair↗
NASA NTRS1971

Study of bonding methods for flip chip and beam leaded devices

The results are presented of a comprehensive study and evaluation for the bonding of flip chip and beam leaded devices onto hybrid microcircuit substrates used in high reliability space applications. The program included the evaluation of aluminum flip chips, solder (silver/tin) bump chips, gold beam leaded devices, and aluminum beam leaded devices.

Rudd, H. C.↗
NASA NTRS1985

A laser plotting system for VLSI chip layouts

One of the most time consuming facets of custom Very Large Scale Integration (VLSI) design is obtaining hardcopy plots of the mask geometries of cells and chips. The traditional method of generating these plots is to use a multicolor pen plotter. Pen plotters are inherently slow and the plotting speed increases linearly with the number of edges that must be plotted. A moderate custom chip design at the Jet Propulsion Laboratory (JPL) now consists of more than 200,000 such edges and can take as much as eight hours to plot using a pen plotter. Software is described that was written at JPL to produce similar plots using a laser printer. It is shown that, for rather small layouts, the laser printer can provide nearly instantaneous turnaround. For moderate to large chip designs, the laser printer provides a factor of five or more improvement is speed over pen plotting.

Deutsch, L. J.↗
NASA NTRS1986

A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder

A description of a single VLSI chip for computing syndromes in the (255, 223) Reed-Solomon decoder is presented. The architecture that leads to this single VLSI chip design makes use of the dual basis multiplication algorithm. The same architecture can be applied to design VLSI chips to compute various kinds of number theoretic transforms.

Hsu, I. S.↗