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A prototype coaxial cable bus communication system used in the Trend Monitoring System to interconnect intelligent graphics terminals to a host minicomputer is described. The terminals and host are connected to the bus through a microprocessor-based RF modem termed a Bus Interface Unit (BIU). The BIU hardware and the Carrier Sense Multiple Access Listen-While-Talk protocol used on the network are described.
A fiber optic data bus, using frequency division multiplexing (FDM) is discussed. The use of FDM is motivated by the need to avoid central control of the bus operation. A major difficulty of such a data bus is introduced by the couplers. An efficient low loss access coupler with an asymmetric structure is presented, and manufacturing processes for the coupler are proposed.
The major thrust was to develop a T coupler with very low (0.1 0.2dB) in-line loss. This is essential to any multiaccess bus structure where the word multi implies fifteen or more nodes on the bus, and it is tacitly assumed to be a passive bus. (Reliability considerations tend to exclude the use of active nodes - repeater nodes.)
An upgrade of the transport systems research vehicle (TSRV) experimental flight system retained the original monochrome display system. The original host computer was replaced with a Norden 11/70, a new digital autonomous terminal access communication (DATAC) data bus was installed for data transfer between display system and host, while a new data interface method was required. The new display data interface uses four split phase bipolar (SPBP) serial busses. The DATAC bus uses a shared interface ram (SIR) for intermediate storage of its data transfer. A display interface unit (DIU) was designed and configured to read from and write to the SIR to properly convert the data from parallel to SPBP serial and vice versa. It is found that separation of data for use by each SPBP bus and synchronization of data tranfer throughout the entire experimental flight system are major problems which require solution in DIU design. The techniques used to accomplish these new data interface requirements are described.
Access becomes timed when collisions threaten. Two-mode scheme used to grant terminals access to data bus. Causes bus to alternate between random accessibility and controlled accessibility to optimize performance and adapt to changing data-traffic conditions. Bus is part of 100-Mb/s optical-fiber packet data system.
Means for evaluating data bus architectures and protocols for highly integrated flight control system applications are needed. Described are the criteria and plans to do this by using the NASA/Ames Intelligent Redundant Actuation System (IRAS) experimental set-up. Candidate bus architectures differ from one another in terms of: topology, access control, message transfer schemes, message characteristics, initialization. data flow control, transmission rates, fault tolerance, and time synchronization. The evaluation criteria are developed relative to these features. A preliminary, analytical evaluation of four candidate busses (MIL-STD-1553B, DATAC, Ethernet, and HSIS) is described. A bus must be exercised in a real-time environment to evaluate its dynamic characteristics. A plan for real-time evaluation of these four busses using a combination of hardware and simulation techniques is presented.
Slave microprocessors in multimicroprocessor computing system contains modified circuit cards programmed via bus connecting master processor with slave microprocessors. Enables interactive, microprocessor-based, single-loop control. Confers ability to load and run program from master/slave bus, without need for microprocessor development station. Tristate buffers latch all data and information on status. Slave central processing unit never connected directly to bus.
The AI Bus architecture is layered, distributed object oriented framework developed to support the requirements of advanced technology programs for an order of magnitude improvement in software costs. The consequent need for highly autonomous computer systems, adaptable to new technology advances over a long lifespan, led to the design of an open architecture and toolbox for building large scale, robust, production quality systems. The AI Bus accommodates a mix of knowledge based and conventional components, running on heterogeneous, distributed real world and testbed environment. The concepts and design is described of the AI Bus architecture and its current implementation status as a Unix C++ library or reusable objects. Each high level semiautonomous agent process consists of a number of knowledge sources together with interagent communication mechanisms based on shared blackboards and message passing acquaintances. Standard interfaces and protocols are followed for combining and validating subsystems. Dynamic probes or demons provide an event driven means for providing active objects with shared access to resources, and each other, while not violating their security.
The MIL-STD-1773 Fiber Optic Data Bus as implemented in the GSFC Small Explorer Data System (SEDS) for the Small Explorer Program is described. It provides an overview of the SEDS MIL-STD-1773 bus components system design considerations, reliability figures, acceptance and qualification testing requirements, radiation requirements and tests, error handling considerations, and component heritage. The first mission using the bus will be launched in June of 1992.
The thrust of this project was to design not a single spacecraft, but to design a multimission bus capable of supporting several current payloads and unnamed, unspecified future payloads. Spiraling costs of spacecraft and shrinking defense budgets necessitated a fresh look at the feasibility of a multimission spacecraft bus. The design team chose two very diverse and different payloads, and along with them two vastly different orbits, to show that multimission spacecraft buses are an area where indeed more research and effort needs to be made. Tradeoffs, of course, were made throughout the design, but optimization of subsystem components limited weight and volume penalties, performance degradation, and reliability concerns. Simplicity was chosen over more complex, sophisticated and usually more efficient designs. Cost of individual subsystem components was not a primary concern in the design phase, but every effort was made to chose flight tested and flight proven hardware. Significant cost savings could be realized if a standard spacecraft bus was indeed designed and purchased in finite quantities.
The Naval Postgraduate School Advanced Design Project sponsored by the Universities Space Research Association Advanced Design Program is a multipurpose satellite bus (MPS). The design was initiated from a Statement of Work (SOW) developed by the Defense Advanced Research Projects Agency (DARPA). The SOW called for a 'proposal to design a small, low-cost, lightweight, general purpose spacecraft bus capable of accommodating any of a variety of mission payloads. Typical payloads envisioned include those associated with meteorological, communication, surveillance and tracking, target location, and navigation mission areas.' The design project investigates two dissimilar missions, a meteorological payload and a communications payload, mated with a single spacecraft bus with minimal modifications. The MPS is designed for launch aboard the Pegasus Air Launched Vehicle (ALV) or the Taurus Standard Small Launch Vehicle (SSLV).
IBM-compatible personal computer used instead of logic analyzer or other special instrument to monitor IEEE-488 interface data bus that interconnects various pieces of laboratory equipment. Needed is short program for computer, commercial general-purpose interface bus circuit card, and adapter cable to link card to bus. Software available in Ada or Quick Basic language.
The FM08 style fuse is specified to interrupt an overcurrent of up to 300 A in a bus of up to 125 VDC, but this applies only when its barrel is filled with air. When placed into a space-grade vacuum, the FM08 style fuse exhausts its air within a year. Then, the probability of an enduring arc is high for all ratings when the bus is above 75 VDC, and the overcurrent is large. The arc endures until something else interrupts the current. The fuse can violently eject metal vapor or other material during the sustained arcing. The evacuated FM08 does not develop a sustained arc when interrupted in a bus of 38 VDC or less, at least when there is little inductance in the circuit. This is consistent with its successful use in many spacecraft having buses in the range 24 to 36 volts.
Nanosatellites operating singly or in clusters are anticipated for future space science missions. To implement this new communications paradigm, we are approaching cluster communications by first developing an infrared (IR) intra-craft wireless bus capability, following initially the MIL-STD-1553B protocol. Benefits of an IR wireless bus are low mass, size, power, and cost, simplicity of implementation, ease of use, minimum EMI, and efficient and reliable data transfer. Our goals are to maximize the reliable link margin in order to afford greater flexibility in receiver placement, which will ease technology insertion. We have developed a concept demonstration using a high-speed visible-band silicon PIN photodiode and a high-efficiency visible LED operating at a data rate up to 4 Mb/sec. In designing an internal IR wireless bus, we have characterized various candidate materials, emitters, and geometries, assuming a single reflection. Thus, we have measured the bidirectional reflectance distribution function (BRDF) for five different materials characteristic of typical spacecraft structures, which range from nearly Lambertian to highly specular. We have fit our data to empirical BRDF functions and modeled the detected irradiance anywhere in the plane of incidence for a divergent (LED) emitter. We have also determined the angular limits on the link geometry to remain within the required bit error rate by determining the received signal-to-noise ratio (SNR) for minimum values of irradiance received at the detector.
A computer simulation of a flywheel energy storage single axis attitude control system is described. The simulation models hardware which will be experimentally tested in the future. This hardware consists of two counter rotating flywheels mounted to an air table. The air table allows one axis of rotational motion. An inertia DC bus coordinator is set forth that allows the two control problems, bus regulation and attitude control, to be separated. Simulation results are presented with a previously derived flywheel bus regulator and a simple PID attitude controller.
Navistar International Transportation Corporation, Chicago, IL, used three separate NASA-developed technologies in the design and testing of their 3000 Series Bus Chassis which was developed expressly for school bus applications. For structural analysis, they used the MSC/NASTRAN program which mathematically analyzes a design and predicts how it will hold up under stress. They also used the SPATE 9000 system for non-contact measurement of stress, load transfer mechanisms, detection of hidden flaws, and monitoring structural changes during fatigue testing. SPATE 9000 was based on infrared stress measurement technology developed by Langley Research Center. They also employed the Wyle Ride Quality Meter, which was developed by Langley to aid in passenger aircraft design by providing an accurate measurement of ride vibration and sound level. These numbers translate into a subjective discomfort level index. These technologies contribute to the company's 45-48 percent share of the school bus chassis market.
This paper discusses the formulation and execution of a laboratory test of the electrical interfaces between multiple atmospheric science instruments and the spacecraft bus that carries them. The testing, performed in 2002, used engineering models of the instruments that will be flown on the Aura s p a c m and of the Aura spacecraft bus electronics. Aura is one of NASA's Earth Observing System @OS) Program missions managed by the Goddard Space Flight Center. The test was designed to evaluate the complex interfaces in the spacecraft and instrument command and data handling (C&DH) subsystems prior to integration of the complete flight instruments on the spacecraft. A problem discovered during (and not before) the flight hardware integration phase can cause significant cost and schedule impacts. The testing successfully surfaced problems and led to their resolution before the full-up integration phase, saving significant cost and schedule time. This approach could be used on future environmental satellite programs involving multiple, complex scientific instruments being integrated onto a bus.
This paper discusses the formulation and execution of a laboratory test of the electrical interfaces between multiple atmospheric scientific instruments and the spacecraft bus that carries them. The testing, performed in 2002, used engineering models of the instruments and the Aura spacecraft bus electronics. Aura is one of NASA s Earth Observatory System missions. The test was designed to evaluate the complex interfaces in the command and data handling subsystems prior to integration of the complete flight instruments on the spacecraft. A problem discovered during the flight integration phase of the observatory can cause significant cost and schedule impacts. The tests successfully revealed problems and led to their resolution before the full-up integration phase, saving significant cost and schedule. This approach could be beneficial for future environmental satellite programs involving the integration of multiple, complex scientific instruments onto a spacecraft bus.