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Planetary probe conical scanning system, signal processing, S-band power amplifier survey, modulation and bit synchronization, antenna temperature, and trajectory perturbations
Apollo ranging code with phase locked loop for bit synchronization, plotting SNR vs error probability and acquisition time
Computer programs for Omega data conversion, summary, and preparation for distribution are presented. Program logic and sample data formats are included, along with operational instructions for each program. Flight data (or data collected in flight format in the laboratory) is provided by the Ohio University Omega receiver base in the form of 6-bit binary words representing the phase of an Omega station with respect to the receiver's local clock. All eight Omega stations are measured in each 10-second Omega time frame. In addition, an event-marker bit and a time-slot D synchronizing bit are recorded. Program FDCON is used to remove data from the flight recorder tape and place it on data-processing cards for later use. Program FDSUM provides for computer plotting of selected LOP's, for single-station phase plots, and for printout of basic signal statistics for each Omega channel. Mean phase and standard deviation are printed, along with data from which a phase distribution can be plotted for each Omega station. Program DACOP simply copies the Omega data deck a controlled number of times, for distribution to users.
The primary accomplishments have been in the analysis and simulation of receivers and bit synchronizers. It has been discovered that tracking rate effects play, a rather fundamental role in both receiver and synchronizer performance, but that data relating to recorder time-base-error, for the proper characterization of this phenomenon, is in rather short supply. It is possible to obtain operationally useful tape recorder time-base-error data from high signal-to-noise ratio tapes using synchronizers with relatively wideband tracking loops. Low signal-to-noise ratio tapes examined in the same way would not be synchronizable. Additional areas of interest covered are receiver false lock, cycle slipping, and other unusual phenomena, which have been described to some extent in this and earlier reports and simulated during the study.
Various aspects of the shuttle orbiter S-band network communication system, the S-band payload communication system, and the Ku-band communication system are considered. A method is proposed for obtaining more accurate S-band antenna patterns of the actual shuttle orbiter vehicle during flight because the preliminary antenna patterns using mock-ups are not realistic that they do not include the effects of additional appendages such as wings and tail structures. The Ku-band communication system is discussed especially the TDRS antenna pointing accuracy with respect to the orbiter and the modifications required and resulting performance characteristics of the convolutionally encoded high data rate return link to maintain bit synchronizer lock on the ground. The TDRS user constraints on data bit clock jitter and data asymmetry on unbalanced QPSK with noisy phase references are included. The S-band payload communication system study is outlined including the advantages and experimental results of a peak regulator design built and evaluated by Axiomatrix for the bent-pipe link versus the existing RMS-type regulator. The nominal sweep rate for the deep-space transponder of 250 Hz/s, and effects of phase noise on the performance of a communication system are analyzed.
Data demodulator for automatic sync acquisition provides an automatic means for obtaining initial word and bit synchronization in a pulse-code-modulated/phase-shift-keyed digital communications system.
As a result of several unique factors, the 2 MHz data channel which carries science data from the various experiments aboard the Space Shuttle through the Tracking and Data Relay Satellite System (TDRSS) lacks sufficient bit transition density to satisfy the bit synchronizer requirements at the ground station. It is noted that six encoding techniques were examined, and all but one, a PN cover sequence (Reset Bit Scrambler) were dismissed because of incompatibility with system constraints. The rationale behind the particular PN sequence chosen, the way it was truncated, and the new sequence properties are presented. The properties of the raw data stream are analyzed, as are the encoded sequence properties, including transition density. Diagrams of the encoder and decoder are included.
The design and performance of the high-density digital recorder (HDDR) developed for use at the NASA centers (KSC, JSC, and GSFC) and at the JPL to store and retrieve 50-Mb/s PCM data streams from the Spacelab experiments are reported. The recording reproduction, and transport requirements are reviewed; and the design solutions adopted in the final version of the HDDR are described, incuding three-position-modulation and Y-phase encoding, microprocessor-controlled automatic bit synchronization and equalization, cyclic-redundancy-check error detection and correction, clock regeneration, data and clock variations, tape-speed control, and EEE-488 remote control. Reliable performance, with bit error rates 1 in 10 to the 10th forward and 1 in 10 to the 9th reverse or better and packing density up to 50 percent greater than that obtainable using conventional codes, is reported after 1.5 years of service.
This paper develops a theory for assessing the tracking performance and designing carrier synchronization loops which are to be matched to an unbalanced QPSK signal design. It is assumed that the power split and the I and Q channel data rates are arbitrary. Bit synchronization is assumed to be unavailable for both carrier reconstruction techniques which have been suggested via MAP estimation theory. Numerical results are presented.
Because of difficulties with the bit detector of the SPA mode 1 channel 3 input port, a new bit synchronizer was required. The two prime candidate designs are described and analyzed. The selected design is a modification of one which utilizes a phase frequency detector to track the received data clock frequency and a mid-bit transition point sample detector to generate a bit timing error (phase error) signal to control the relative phase between the local clock and the local data stream. The model used to calculate the effects of cable attenuation and rise time degradation is discussed.
A hybrid receiver has been designed for the Galileo Project. The receiver, located on the Galileo Orbiter, will autonomously acquire and track signals from the first atmospheric probe of Jupiter as well as demodulate, bit-synchronize, and buffer the telemetry data. The receiver has a conventional RF and LF front end but performs multiple functions digitally under firmware control. It will be a self-acquiring receiver that operates under a large frequency uncertainty; it can accommodate different modulation types, bit rates, and other parameter changes via reprogramming. A breadboard receiver and test set demonstrate a preliminary version of the sequential detection process and verify the hypothesis that a fading channel does not reduce the probability of detection.
Convolutional coding, used to upgrade digital data transmission under adverse signal conditions, has been improved by a method which ensures data transitions, permitting bit synchronizer operation at lower signal levels. Method also increases decoding ability by removing ambiguous condition.
Autocorrelation functions, power spectral density, bandwidth, and bit synchronization efficiency for PCM code formats
Phase noise and cycle slip optimization of steady state digital data transition tracking loop used as bit synchronizer in phase-coherent receiver
Consideration of the problem of selecting a low-pass sampling bandwidth for the digital mechanization of a matched-filter bit-synchronizer combination. An attempt is made to determine how large a data rate can be provided for a fixed sampling rate (limited by hardware considerations on the sampling device) without paying an excessive penalty in SNR performance.
Bit-synchronizers utilize all-digital phase-lock loops that are referenced to a high frequency digital clock. Phase-lock loop of first design acquires frequency within nominal range and tracks phase; second design is modified for random binary data by addition of simple transition detector; and third design acquires frequency over wide dynamic range.
Computer software was developed which makes it possible to use any general purpose computer with A/D conversion capability as a PSK receiver for low data rate telemetry processing. Carrier tracking, bit synchronization, and matched filter detection are all performed digitally. To aid in the implementation of optimum computer processors, a study of general digital processing techniques was performed which emphasized various techniques for digitizing general analog systems. In particular, the phase-locked loop was extensively analyzed as a typical non-linear communication element. Bayesian estimation techniques for PSK demodulation were studied. A hardware implementation of the digital Costas loop was developed.
Results are presented of a comprehensive study of the performance of Viterbi-decoded convolutional codes in the presence of nonideal carrier tracking and bit synchronization. A constraint length 7, rate 1/3 convolutional code and parameters suitable for the space shuttle coded communications links are used. Mathematical models are developed and theoretical and simulation results are obtained to determine the tracking and acquisition performance of the system. Pseudorandom sequence spread spectrum techniques are also considered to minimize potential degradation caused by multipath.