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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Predicting Lifetimes Of CMOS ASIC's From Test Data

Concise report discusses recent developments in use of semiempirical mathematical models to predict rates of failure and operating lifetimes of complementary metal oxide/semiconductor (CMOS) application-specific integrated circuits (ASIC's). Each model represents specific mechanism of failure. Once failure mechanisms and models relevant to given ASIC chosen, adjustable parameters in models fitted to life-test data acquired from representative integrated-circuit structures on test coupons fabricated along with ASIC's. Then design parameters of ASIC's incorporated into models, and models yield lifetimes.

Buehler, Martin G.↗
NASA NTRS1994

Estimating Delays In ASIC's

Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.

Burke, Gary↗
DOE OSTI2023

Design and performance of the Fermilab Constant Fraction Discriminator ASIC

Here, we present the design and performance characterization results of the novel Fermilab Constant Fraction Discriminator ASIC (FCFD) developed to readout low gain avalanche detector (LGAD) signals by directly using a constant fraction discriminator (CFD) to measure signal arrival time. Silicon detectors with time resolutions less than 30ps will play a critical role in future collider experiments, and LGADs have been demonstrated to provide the required time resolution and radiation tolerance for many such applications. The FCFD has a specially designed discriminator that is robust against amplitude variations of the signal from the LGAD that normally requires an additional correction step when using a traditional leading edge discriminator. The application of the CFD directly in the ASIC promises to be more reliable and reduces the complication of evolving time-walk corrections throughout the operational lifetime of the detector system. We will present a summary of the measured performance of the FCFD for input signals generated by internal charge injection, LGAD signals from an infrared laser, and LGAD signals from minimum-ionizing particles. The mean time response for LGAD signals with charge ranging between 5 and 26 fC has been measured to vary no more than 10ps, orders of magnitude more stable than an uncorrected leading edge discriminator based measurement, and effectively removes the need for any additional time-walk correction. The measured contribution to the time resolution from the FCFD ASIC is found to be 10ps for signals with charge above 20fC.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2007

Improved On-Chip Measurement of Delay in an FPGA or ASIC

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Chen, Yuan↗
DOE OSTI2020

Design and Testing of the Address in Real-Time Data Driver Card for the Micromegas Detector of the ATLAS New Small Wheel Upgrade

The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data in the Micro-Mesh Gaseous Structure (Micromegas) detector of the ATLAS New Small Wheel (NSW) upgrade. The Address in Real Time (ART) signals are generated by the front-end ASIC, named VMM chip, to indicate the address of the first above-threshold event. A custom ASIC (ART ASIC) is designed to receive the ART signals from the VMM chip and implement the hit-selection. The processed data from the ART ASIC will be transmitted out of the NSW through the GBTx serializer, the unidirectional Versatile Twin Transmitter (VTTx) and fiber optical links. The ART signal is critical for the ATLAS experiment trigger selection thus the performance and stability of the ADDC is very important. To ensure extensive testing of the ADDC, an FPGA Mezzanine Card (FMC) based testing platform and a special designed firmware/software are developed. We find that this test platform works with the commercial Xilinx VC707 FPGA development kit, independent of the other electronics of the NSW it can test all the functions of the ADDC and its long-term stability. This paper will introduce the design, testing procedure and results of the ADDC and the FMC testing platform.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specific integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifiers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verified using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond Timing

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specifc integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verifed using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
NASA NTRS2017

Modeling and Measuring Charge-Sharing in Hard X-ray Imagers Using HEXITEC CdTe Detectors

The Rutherford Appleton Laboratory's HEXITEC ASIC has been designed to provide fine pixelated X-ray spectroscopic imaging in combination with a CdTe or CZT detector layer. Although HEXITEC's small pixels enable higher spatial resolution as well as higher spectral resolution via the small-pixel effect, they also increase the probability of charge sharing, a process which degrades spectral performance by dividing the charge induced by a single photon among multiple pixels. In this paper, we investigate the effect of this process on a continuum X-ray spectrum below the Cd and Te fluorescence energies (23 keV). This is done by comparing laboratory measurements with simulations performed with a custom designed model of the HEXITEC ASIC. We find that the simulations closely match the observations implying that we have an adequate understanding of both charge sharing and the HEXITEC ASIC itself. These results can be used to predict the distortion of a spectrum measured with HEXITEC and will help determine to what extent it can be corrected. They also show that models like this one are important tools in developing and interpreting observations from ASICs like HEXITEC.

Ryan, Daniel F.↗
DOE OSTI2022

Design and Challenges of Edge Computing ASICs on Front-End Electronics

In situ or hardware-embedded data processing of raw signals, close to their source, in radiation detectors is expected to provide dramatic improvements in data quality and volumes. However, the implementation of artificial neural networks (ANNs) in the front-end electronics, and the design of custom integrated circuits (ASICs), comes with challenges. In addition, detectors have to operate with limited power budget and implement complex functionalities in a very dense space. They often are exposed to extreme conditions as they work in high-radiation environments and/or cryogenic temperatures. This paper presents examples of applications and design methodologies for in-situ ANNs, along with the challenges of retaining the fidelity of the trained networks. For illustration, we use the problem of estimating the energy deposited by the radiation from digitized waveforms. The proposed implementation starts with an ML algorithm trained in Qkeras and eventually leads to an equivalent ASIC implementation. The associated design challenges in realizing energy and area efficient implementations in CMOS processes are reviewed. Novel approaches that employ hybrid technologies (combination of CMOS with memristors), in-memory computing models, and bio-inspired spiking neural networks are also highlighted

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Radiation-hard miniature optical engine with high bandwidth

Future silicon trackers will be operated in an intense radiation environment and require large volumes of data to be transmitted off detector. In addition, the optical modules must be of low mass in order to limit multiple scattering and nuclear interactions that would degrade the overall performance of the detector. Here, we present a miniature optical engine that satisfies these constraints. The optical engine consists of an ASIC driving a VCSEL (Vertical Cavity Surface Emitting Laser) array in an optical package. Two ASICs are designed to operate a 12-channel VCSEL array at 1.28 or 5.12 Gb/s per channel, which yields a total data rate of up to 60 Gb/s. The core transistors are fabricated in a 65 nm CMOS process which enhance the radiation-hardness. Each channel contains equalizer (CTLE) and clock-data recovery circuits (CDR) so that the ASIC can restore the highly distorted electrical signal after propagating through several meters of cables of small diameter. The equalizer, CDR, and VCSEL driver are configured via a digital I 2 C chip interface with triple redundant memory to mitigate single event upset (SEU) effects. The bias and modulation currents are controlled by a digital-to-analog converter (DAC). We present the design of the circuit together with the results of the simulations and preliminary measurements.

47 OTHER INSTRUMENTATION↗
NASA NTRS2003

Command Interface ASIC - Analog Interface ASIC Chip Set

A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B of the I(sup 2)C buses are electrically isolated from each other (see figure). They are also isolated from the CIA by use of transformer coupling of signals between the AIA blocks and the CIA.

Ruiz, Baldes↗
NASA NTRS1993

Flexible high speed CODEC

HARRIS, under contract with NASA Lewis, has developed a hard decision BCH (Bose-Chaudhuri-Hocquenghem) triple error correcting block CODEC ASIC, that can be used in either a bursted or continuous mode. the ASIC contains both encoder and decoder functions, programmable lock thresholds, and PSK related functions. The CODEC provides up to 4 dB of coding gain for data rates up to 300 Mbps. The overhead is selectable from 7/8 to 15/16 resulting in minimal band spreading, for a given BER. Many of the internal calculations are brought out enabling the CODEC to be incorporated in more complex designs. The ASIC has been tested in BPSK, QPSK and 16-ary PSK link simulators and found to perform to within 0.1 dB of theory for BER's of 10(exp -2) to 10(exp -9). The ASIC itself, being a hard decision CODEC, is not limited to PSK modulation formats. Unlike most hard decision CODEC's, the HARRIS CODEC doesn't upgrade BER performance significantly at high BER's but rather becomes transparent.

Wernlund, James V.↗
NASA NTRS1993

An ASIC memory buffer controller for a high speed disk system

The need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.

Hodson, Robert F.↗
DOE OSTI2023

Experimental results from the characterization of a 32-channels mixed-signal processor for the GAPS experiment

This work describes the experimental results obtained from the characterization of a 32-channels readout ASIC that is the core of a module composed by 4 Lithium-drifted Silicon, Si(Li), detectors. The module is the building block of a tracker in an upcoming balloon experiment. The activity is carried out within the General AntiParticle Spectrometer (GAPS) international collaboration, whose objective is the indirect detection of dark matter through the detection of antiparticles present in cosmic rays at low energies. The balloon flight is foreseen in 2024 from the McMurdo station in Antarctica. The ASIC is designed in a 180 nm CMOS technology and has 32 low-noise analog readout channels featuring a dynamic compression of the signal, an 11-bit SAR ADC, and a digital back-end section responsible for channel setting and for sending digital information to the data acquisition system of the tracker. This work has a twofold goal: it intends on the one hand to verify the performance of the circuit, on the other to select at least 300 good samples to be used for the assembly of the GAPS Si(Li) tracker.

Riceputi, Elisa↗
NASA NTRS1992

Spacecraft optical disk recorder memory buffer control

The goal of this project is to develop an Application Specific Integrated Circuit (ASIC) for use in the control electronics of the Spacecraft Optical Disk Recorder (SODR). Specifically, this project is to design an extendable memory buffer controller ASIC for rate matching between a system Input/Output port and the SODR's device interface. The aforementioned goal can be partitioned into the following sub-goals: (1) completion of ASIC design and simulation (on-going via ASEE fellowship); (2) ASIC Fabrication (at ASIC manufacturer); and (3) ASIC Testing (NASA/LaRC, Christopher Newport University).

Hodson, Robert F.↗
NASA NTRS2005

Integrated low power digital gyro control electronics

Embodiments of the invention generally encompass a digital, application specific integrated circuit (ASIC) has been designed to perform excitation of a selected mode within a vibratory rate gyroscope, damping, or force-rebalance, of other modes within the sensor, and signal demodulation of the in-phase and quadrature components of the signal containing the angular rate information. The ASIC filters dedicated to each channel may be individually programmed to accommodate different rate sensor designs/technology or variations within the same class of sensors. The ASIC architecture employs a low-power design, making the ASIC, particularly suitable for use in power-sensitive applications.

M'Closkey, Robert↗
DOE OSTI2024

Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals

This paper presents design details and measurement results of LArASIC, a front-end application specific integrated circuit (ASIC) designed for low-noise readout of charge signals generated in neutrino study experiments within liquid argon time projection chambers. LArASIC comprises of 16-channels of programmable charge amplification and pulse shaping stages that provide a voltage readout proportional to the input charge and was optimized for operation at liquid argon temperature, i.e., 89 K. The chip was fabricated in a 180 nm CMOS process. Measurements at liquid nitrogen temperature, i.e., 77 K, indicate that the channel outputs have high linearity (INL < 0.1%) within the operating range, an equivalent noise charge of 534 electrons for a peaking time of 1 µs and a detector capacitance of 150 pF, and a worst-case inter-channel cross-talk of 0.35%. The paper also presents design choices made in the process of migrating LArASIC to CHARMS, an ASIC to be fabricated in a 65 nm process that includes all features provided by LArASIC, along with additional digital programmability for improved robustness and flexibility. CHARMS is intended for use in future high-energy physics experiments that require high-resolution charge or light readout with shorter pulse peaking times.

47 OTHER INSTRUMENTATION↗
NASA NTRS1997

Case Study of the Design of a Viterbi Decoder

This paper describes the design of an ASIC performing the Viterbi decoder function with a constraint length of 15 and a speed of 4.4 Mb/s. The architecture of the chip is described, as well as the design challenges which were overcome. The author also describes the successful application of the design system.

Viterbi decoder ASIC microprocessor design↗