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At least 523 records · Page 29

A Parallel Multilevel Spectral Element Scheme

A parallel multilevel strategy is developed using spectral (p) finite elements. Hierarchic bases are particularly well suited since the element matrices and vectors are nested and the multilevel projections easiliy performed. Since the basis degree is used to specify the multigrid level, an EBE strategy is natural br the multilevel technique. Results are presented for two candidate nonlinear elliptic transport problems: the augmented drift-diffusion equations of semiconductor device modeling and the stream function-vorticity equations of incompressible fluid dynamics.

Davis, M. B.↗

Dopant Incorporation Efficiency in CVD Silicon Carbide Epilayers

In order to ensure reproducible and reliable SiC semiconductor device characteristics, controlled dopant incorporation must be accomplished. Some of the many factors which greatly influence dopant incorporation are the site-competition effect, SiC(0001) substrate polarity, substrate temperature, and the dopant-source reactor concentration. In this paper, dopant incorporation is considered and compared for various dopants in the context of dopant incorporation efficiency. By using secondary ion mass spectrometry (SIMS), the relative dopant incorporation efficiencies were calculated by dividing the SIMS determined dopant concentration in the resulting epitaxial layer by the intentional gas phase dopant concentration used during the SiC CVD. Specifically, the relative magnitudes of dopant incorporation efficiencies for nitrogen, phosphorus, and boron in 6H-SiC (0001) Si-face epitaxial layers are compared as a function of the site-competition effect and the dopant-source reactor concentrations. This serves as a first approximation for comparison of the relative 'doping potencies' of some common dopants used in SiC CVD epitaxial growth.

Larkin, D. J.↗

Ballistic-Electron-Emission-Microscopy of Strained Si(sub 1-x)Ge(sub x) Layers

Ballistic-electron-emission microscopy (BEEM) has been used to investigate the effects of strain on Si(sub 1-x)Ge(sub x) alloys. Lifting of the degeneracy of the conduction-band minimum of Si(sub 1-x)Ge(sub x), due to lattice deformation has been directly measured by application of BEEM spectroscopy to Ag/Si structures. Experimental values for this conduction-band splitting agree well with calculations. In addition, an unexpected heterogeneity in the strain of the Si(sub 1-x)Ge(sub x) layer is introduced by deposition of Au. This effect, not observed with Ag, is attributed to species interdiffusion and has important implications for metal-semiconductor devices based oil pseudomorphic Si(sub 1-x)Ge(sub x)/Si material systems.

Bell, L. D.↗

Nano-Satellite Avionics

Abstract NASA's Goddard Space Flight Center (GSFC) is currently developing a new class of satellites called the nano-satellite (nano-sat). A major objective of this development effort is to provide the technology required to enable a constellation of tens to hundreds of nano-satellites to make both remote and in-situ measurements from space. The Nano-sat will be a spacecraft weighing a maximum of 10 kg, including the propellant mass, and producing at least 5 Watts of power to operate the spacecraft. The electronics are required to survive a total radiation dose rate of 100 krads for a mission lifetime of two years. There are many unique challenges that must be met in order to develop the avionics for such a spacecraft. The first challenge is to develop an architecture that will operate on the allotted 5 Watts and meet the diverging requirements of multiple missions. This architecture will need to incorporate a multitude of new advanced microelectronic technologies. The microelectronics developed must be a modular and scalable packaging of technology to solve the problem of developing a solution to both reduce cost and meet the requirements of various missions. This development will utilize the most cost effective approach, whether infusing commercially driven semiconductor devices into spacecraft applications or partnering with industry to design and develop low cost, low power, low mass, and high capacity data processing devices. This paper will discuss the nano-sat architecture and the major technologies that will be developed. The major technologies that will be covered include: (1) Light weight Low Power Electronics Packaging, (2) Radiation Hard/Tolerant, Low Power Processing Platforms, (3) High capacity Low Power Memory Systems (4) Radiation Hard reconfiguragble field programmable gate array (rFPGA)

Culver, Harry↗

An Acoustic Charge Transport Imager for High Definition Television

This project, over its term, included funding to a variety of companies and organizations. In addition to Georgia Tech these included Florida Atlantic University with Dr. William E. Glenn as the P.I., Kodak with Mr. Mike Richardson as the P.I. and M.I.T./Polaroid with Dr. Richard Solomon as the P.I. The focus of the work conducted by these organizations was the development of camera hardware for High Definition Television (HDTV). The focus of the research at Georgia Tech was the development of new semiconductor technology to achieve a next generation solid state imager chip that would operate at a high frame rate (I 70 frames per second), operate at low light levels (via the use of avalanche photodiodes as the detector element) and contain 2 million pixels. The actual cost required to create this new semiconductor technology was probably at least 5 or 6 times the investment made under this program and hence we fell short of achieving this rather grand goal. We did, however, produce a number of spin-off technologies as a result of our efforts. These include, among others, improved avalanche photodiode structures, significant advancement of the state of understanding of ZnO/GaAs structures and significant contributions to the analysis of general GaAs semiconductor devices and the design of Surface Acoustic Wave resonator filters for wireless communication. More of these will be described in the report. The work conducted at the partner sites resulted in the development of 4 prototype HDTV cameras. The HDTV camera developed by Kodak uses the Kodak KAI-2091M high- definition monochrome image sensor. This progressively-scanned charge-coupled device (CCD) can operate at video frame rates and has 9 gm square pixels. The photosensitive area has a 16:9 aspect ratio and is consistent with the "Common Image Format" (CIF). It features an active image area of 1928 horizontal by 1084 vertical pixels and has a 55% fill factor. The camera is designed to operate in continuous mode with an output data rate of 5MHz, which gives a maximum frame rate of 4 frames per second. The MIT/Polaroid group developed two cameras under this program. The cameras have effectively four times the current video spatial resolution and at 60 frames per second are double the normal video frame rate.

Hunt, William D.↗

A Smoothed Boundary Condition for Reducing Nonphysical Field Effects

In this paper, we examine the problem associated with abruptly mixing boundary conditions in the context of a two-dimensional semiconductor device simulator. Explicitly, this paper addresses the transition between an ohmic-type Dirichlet condition and a passivated Neumann boundary. In the traditional setting, the details or the transition between the two boundary types are not addressed and an abrupt transition is assumed. Subsequently, the calculated observables (most notably the potential) exhibit discontinuous derivatives near the surface at the point where the boundary type switches. This paper proposes an alternative condition which models the progression between the two boundary types through the use of a finite length, smoothed boundary whereby the numerical discontinuities are eliminated. The physical and mathematical basis for this smoothed boundary condition is discussed and examples of the technique's implementation given. It is found that the proposed boundary condition is numerically efficient and can be implemented in pre-existing device simulators with relative ease.

Smith, Arlynn W.↗

Development of Electronics for Low Temperature Space Missions

The operation of electronic systems at cryogenic temperatures is anticipated for many future NASA space missions such as deep space probes and planetary surface exploration. For example, an unheated interplanetary probe launched to explore the rings of Saturn would reach an average temperature near Saturn of about -183 C. In addition to surviving the deep space harsh environment, electronics capable of low temperature operation would contribute to improving circuit performance, increasing system efficiency, and reducing payload development and launch costs. Terrestrial applications where components and systems must operate in low temperature environments include cryogenic instrumentation, superconducting magnetic energy storage, magnetic levitation transportation system, and arctic exploration. An on-going research and development program on low temperature electronics at the NASA Glenn Research Center focuses on the development of efficient power systems capable of surviving and exploiting the advantages of low temperature environments. Inhouse efforts include the design, fabrication, and characterization of low temperature power systems and the development of supporting technologies for low temperature operations, such as dielectric and insulating materials, semiconductor devices, passive power components, opto-electronic devices, as well as packaging and integration of the developed components into prototype flight hardware.

Patterson, Richard L.↗

A Fresh Look at Coupled-Oscillator Spatial Power Combining

Quasi-optical oscillators were proposed a little more than ten years ago as a means of developing the power levels needed for applications at millimeter frequencies using large numbers of individual semiconductor devices each of which produces only a modest amount of power [J.W. Mink, IEEE Trans. MTT., vol. 34, p. 273, 19861. An operating system was demonstrated soon after [Z.B. Popovic et. al, Int. J. Infrared and Millimeter Waves, v. 9, p. 647, 1988] in the form of a so-called grid oscillator. This device constituted a rectangular array of oscillating devices that are mutually coupled so that they oscillator coherently. The interconnecting lines in one direction serve as radiators so that the oscillators radiate directly, and the radiated fields add. Subsequently, coupled oscillators using resonant transmission line lengths was demonstrated by Mortazawi and Itoh [IEEE Trans. MTT., vol. 38, p. 86,1990). In recent work, coupled-oscillator power combiners have received less attention, with amplifier/combiners receiving more attention. Specific weaknesses of spatial-combining oscillators have motivated this transition. Namely, the oscillators employ low-Q resonators (resulting in low signal quality) and no clear means of modulation has been identified until recently. In this presentation, we review coupled-oscillator combiners in broad terms, indicating the features that make particular systems viable. We indicate how these features can be reconciled to functional requirements for system applications. Comparisons are drawn between two approaches to obtain mutual coupling: One employs low-Q oscillator circuits at each site, with concomitantly high propensity for the oscillators to couple. The other approach employs moderate-Q oscillators at each site with the concomitant requirement to tune the oscillators so that they share a range of frequencies over which they can couple and lock. In either case, precise frequency control and modulation can be achieved through locking to an external frequency source that ensures high quality signals. A recent development in coupled-oscillator arrays provides a means for beam-steering the radiation field of coupled oscillators through de-tuning of the edge elements in the array. This detuning introduces a progressive phase shift across the oscillator array. This 0 suggests architectures that can replace the functionality of a phased array without the cost 0 incurred by phase shifters. A comprehensive theory of the phase interactions among devices in such arrays is under development [e.g., Pogorzelski, York, and Maccarini, 1998 AP-S International Symposium, Atlanta, GA. June, 19981.

Pearson, L.W.↗

Development of Electronics for Low-Temperature Space Missions

Electronic systems that are capable of operating at cryogenic temperatures will be needed for many future NASA space missions, including deep space probes and spacecraft for planetary surface exploration. In addition to being able to survive the harsh deep space environment, low-temperature electronics would help improve circuit performance, increase system efficiency, and reduce payload development and launch costs. Terrestrial applications where components and systems must operate in low-temperature environments include cryogenic instrumentation, superconducting magnetic energy storage, magnetic levitation transportation systems, and arctic exploration. An ongoing research and development project for the design, fabrication, and characterization of low-temperature electronics and supporting technologies at NASA Glenn Research Center focuses on efficient power systems capable of surviving in and exploiting the advantages of low-temperature environments. Supporting technologies include dielectric and insulating materials, semiconductor devices, passive power components, optoelectronic devices, and packaging and integration of the developed components into prototype flight hardware. An overview of the project is presented, including a description of the test facilities, a discussion of selected data from component testing, and a presentation of ongoing research activities being performed in collaboration with various organizations.

Patterson, Richard L.↗

Quantum Dots Based Rad-Hard Computing and Sensors

Quantum Dots (QDs) are solid-state structures made of semiconductors or metals that confine a small number of electrons into a small space. The confinement of electrons is achieved by the placement of some insulating material(s) around a central, well-conducting region. Thus, they can be viewed as artificial atoms. They therefore represent the ultimate limit of the semiconductor device scaling. Additional information is contained in the original extended abstract.

Fijany, A.↗

Electronics for Extreme Environments

Most of the NASA missions involve extreme environments comprising radiation and low or high temperatures. Current practice of providing friendly ambient operating environment to electronics costs considerable power and mass (for shielding). Immediate missions such as the Europa orbiter and lander and Mars landers require the electronics to perform reliably in extreme conditions during the most critical part of the mission. Some other missions planned in the future also involve substantial surface activity in terms of measurements, sample collection, penetration through ice and crust and the analysis of samples. Thus it is extremely critical to develop electronics that could reliably operate under extreme space environments. Silicon On Insulator (SOI) technology is an extremely attractive candidate for NASA's future low power and high speed electronic systems because it offers increased transconductance, decreased sub-threshold slope, reduced short channel effects, elimination of kink effect, enhanced low field mobility, and immunity from radiation induced latch-up. A common belief that semiconductor devices function better at low temperatures is generally true for bulk devices but it does not hold true for deep sub-micron SOI CMOS devices with microscopic device features of 0.25 micrometers and smaller. Various temperature sensitive device parameters and device characteristics have recently been reported in the literature. Behavior of state of the art technology devices under such conditions needs to be evaluated in order to determine possible modifications in the device design for better performance and survivability under extreme environments. Here, we present a unique approach of developing electronics for extreme environments to benefit future NASA missions as described above. This will also benefit other long transit/life time missions such as the solar sail and planetary outposts in which electronics is out open in the unshielded space at the ambient space temperatures and always exposed to radiation. Additional information is contained in the original extended abstract.

Patel, J. U.↗

Novel Vertical Interconnects With 180 Degree Phase Shift for Amplifiers, Filters, and Integrated Antennas

In this paper, novel low loss, wide-band coplanar stripline technology for RF/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semiconductor devices and microelectromechanical systems (MEMS).

Goverdhanam, Kavita↗

On the Fabrication and Behavior of Diamond Microelectromechanical Sensors (DMEMS)

CVD (chemically vapor deposited) diamond films can be processed similar to "conventional" semiconductor device fabrication and as such can be used to achieve microelectromechanical structures (MEMS) also similar to, for example, silicon technology. Very small cantilever beams, membranes, stripes, tips, etc. can be constructed in doped and undoped diamond films and offer an array of choices in diamond with its known superior properties such as elastic modulus, high temperature semiconduction, high thermal conductivity, very low coefficient of expansion and numerous other diamond parameters. This paper will review the construction and behavior of the second generation DMEMS devices comprised as an accelerometer with a diamond diaphragm for use in very high G applications and a diamond pressure sensor for very high temperature and frequency response.

Holmes, K.↗

A Survey of Power Electronics Applications in Aerospace Technologies

The insertion of power electronics in aerospace technologies is becoming widespread. The application of semiconductor devices and electronic converters, as summarized in this paper, includes the International Space Station, satellite power system, and motor drives in 'more electric' technology applied to aircraft, starter/generators and reusable launch vehicles. Flywheels, servo systems embodying electromechanical actuation, and spacecraft on-board electric propulsion are discussed. Continued inroad by power electronics depends on resolving incompatibility of using variable frequency for 400 Hz-operated aircraft equipment. Dual-use electronic modules should reduce system development cost.

Kankam, M. David↗

High Performance Parallel Computational Nanotechnology

At a recent press conference, NASA Administrator Dan Goldin encouraged NASA Ames Research Center to take a lead role in promoting research and development of advanced, high-performance computer technology, including nanotechnology. Manufacturers of leading-edge microprocessors currently perform large-scale simulations in the design and verification of semiconductor devices and microprocessors. Recently, the need for this intensive simulation and modeling analysis has greatly increased, due in part to the ever-increasing complexity of these devices, as well as the lessons of experiences such as the Pentium fiasco. Simulation, modeling, testing, and validation will be even more important for designing molecular computers because of the complex specification of millions of atoms, thousands of assembly steps, as well as the simulation and modeling needed to ensure reliable, robust and efficient fabrication of the molecular devices. The software for this capacity does not exist today, but it can be extrapolated from the software currently used in molecular modeling for other applications: semi-empirical methods, ab initio methods, self-consistent field methods, Hartree-Fock methods, molecular mechanics; and simulation methods for diamondoid structures. In as much as it seems clear that the application of such methods in nanotechnology will require powerful, highly powerful systems, this talk will discuss techniques and issues for performing these types of computations on parallel systems. We will describe system design issues (memory, I/O, mass storage, operating system requirements, special user interface issues, interconnects, bandwidths, and programming languages) involved in parallel methods for scalable classical, semiclassical, quantum, molecular mechanics, and continuum models; molecular nanotechnology computer-aided designs (NanoCAD) techniques; visualization using virtual reality techniques of structural models and assembly sequences; software required to control mini robotic manipulators for positional control; scalable numerical algorithms for reliability, verifications and testability. There appears no fundamental obstacle to simulating molecular compilers and molecular computers on high performance parallel computers, just as the Boeing 777 was simulated on a computer before manufacturing it.

Saini, Subhash↗

Dynamic Load Balancing for Adaptive Unstructured Grids

Dynamic mesh adaptation on unstructured grids is a powerful tool for computing unsteady three-dimensional problems that require grid modifications to efficiently resolve solution features. By locally refining and coarsening the mesh to capture phenomena of interest, such procedures make standard computational methods more cost effective. Highly refined meshes are required to accurately capture shock waves, contact discontinuities, vortices, and shear layers in fluid flow problems. Adaptive meshes have also proved to be useful in several other areas of computational science and engineering like computer vision and graphics, semiconductor device modeling, and structural mechanics. Local mesh adaptation provides the opportunity to obtain solutions that are comparable to those obtained on globally-refined grids but at a much lower cost. Additional information is contained in the original extended abstract.

Biswas, Rupak↗

Computational Nanoelectronics and Nanotechnology at NASA ARC

Both physical and economic considerations indicate that the scaling era of CMOS will run out of steam around the year 2010. However, physical laws also indicate that it is possible to compute at a rate of a billion times present speeds with the expenditure of only one Watt of electrical power. NASA has long-term needs where ultra-small semiconductor devices are needed for critical applications: high performance, low power, compact computers for intelligent autonomous vehicles and Petaflop computing technology are some key examples. To advance the design, development, and production of future generation micro- and nano-devices, IT Modeling and Simulation Group has been started at NASA Ames with a goal to develop an integrated simulation environment that addresses problems related to nanoelectronics and molecular nanotechnology. Overview of nanoelectronics and nanotechnology research activities being carried out at Ames Research Center will be presented. We will also present the vision and the research objectives of the IT Modeling and Simulation Group including the applications of nanoelectronic based devices relevant to NASA missions.

Saini, Subhash↗

Electronics for Deep Space Cryogenic Applications

Deep space probes and planetary exploration missions require electrical power management and control systems that are capable of efficient and reliable operation in very cold temperature environments. Typically, in deep space probes, heating elements are used to keep the spacecraft electronics near room temperature. The utilization of power electronics designed for and operated at low temperature will contribute to increasing efficiency and improving reliability of space power systems. At NASA Glenn Research Center, commercial-off-the-shelf devices as well as developed components are being investigated for potential use at low temperatures. These devices include semiconductor switching devices, magnetics, and capacitors. Integrated circuits such as digital-to-analog and analog-to-digital converters, DC/DC converters, operational amplifiers, and oscillators are also being evaluated. In this paper, results will be presented for selected analog-to-digital converters, oscillators, DC/DC converters, and pulse width modulation (PWM) controllers.

Patterson, R. L.↗