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DOE OSTI2021

A Fabrication Strategy for Reconfigurable Millimeter–Scale Metamaterials

Rather than depending on material composition to primarily dictate performance metrics, metamaterials can leverage geometry to achieve specific properties of interest. For example, reconfigurable metamaterials have enabled programmable shape transformations, tunable mechanical properties, and energy absorption. While several methods exist to fabricate such structures, they often place severe restrictions on manufacturing materials, or require significant manual assembly. Moreover, these arrays are typically composed of unit cells that are either macro–scale or micro–scale in dimension. Here, the fabrication gap is bridged, and laminate manufacturing is used to develop a method for designing reconfigurable metamaterials at the millimeter–scale, that is compatible with a wide range of materials, and that requires minimal manual assembly. In addition to showing the versatility of this fabrication method, how the use of laminate manufacturing affects the behavior of these multi–component arrays is also characterized. To this end, a numerical model that captures the deformations exhibited by the structures is developed, and an analytic model that predicts the strain of the structure under compressive stress is built. Overall, this approach can be leveraged to develop millimeter–scale metamaterials for applications that require reconfigurable materials, such as in the design of tunable acoustics, photonic waveguides, and electromagnetic devices.

36 MATERIALS SCIENCE↗

NASA NTRS2012

Fault-Tolerant, Real-Time, Multi-Core Computer System

A document discusses a fault-tolerant, self-aware, low-power, multi-core computer for space missions with thousands of simple cores, achieving speed through concurrency. The proposed machine decides how to achieve concurrency in real time, rather than depending on programmers. The driving features of the system are simple hardware that is modular in the extreme, with no shared memory, and software with significant runtime reorganizing capability. The document describes a mechanism for moving ongoing computations and data that is based on a functional model of execution. Because there is no shared memory, the processor connects to its neighbors through a high-speed data link. Messages are sent to a neighbor switch, which in turn forwards that message on to its neighbor until reaching the intended destination. Except for the neighbor connections, processors are isolated and independent of each other. The processors on the periphery also connect chip-to-chip, thus building up a large processor net. There is no particular topology to the larger net, as a function at each processor allows it to forward a message in the correct direction. Some chip-to-chip connections are not necessarily nearest neighbors, providing short cuts for some of the longer physical distances. The peripheral processors also provide the connections to sensors, actuators, radios, science instruments, and other devices with which the computer system interacts.

Gostelow, Kim P.↗

NASA NTRS2006

Acceleration of Stereo Correlation in Verilog

To speed up vision processing in low speed, low power devices, embedding FPGA hardware is becoming an effective way to add processing capability. FPGAs offer the ability to flexibly add parallel and/or deeply pipelined computation to embedded processors without adding significantly to the mass and power requirements of an embedded system. This paper will discuss the JPL stereo vision system, and describe how a portion of that system was accelerated by using custom FPGA hardware to process the computationally intensive portions of JPL stereo. The architecture described takes full advantage of the ability of an FPGA to use many small computation elements in parallel. This resulted in a 16 times speedup in real hardware over using a simple linear processor to compute image correlation and disparity.

machine vision↗

NASA NTRS2008

Controller for Driving a Piezoelectric Actuator at Resonance

A digital control system based partly on an extremum-seeking control algorithm tracks the changing resonance frequency of a piezoelectric actuator or an electrically similar electromechanical device that is driven by a sinusoidal excitation signal and is required to be maintained at or near resonance in the presence of uncertain, changing external loads and disturbances. Somewhat more specifically, on the basis of measurements of the performance of the actuator, this system repeatedly estimates the resonance frequency and alters the excitation frequency as needed to keep it at or near the resonance frequency. In the original application for which this controller was developed, the piezoelectric actuator is part of an ultrasonic/sonic drill/corer. Going beyond this application, the underlying principles of design and operation are generally applicable to tracking changing resonance frequencies of heavily perturbed harmonic oscillators. Resonance-frequency-tracking analog electronic circuits are commercially available, but are not adequate for the present purpose for several reasons: The input/output characteristics of analog circuits tend to drift, often necessitating recalibration, especially whenever the same controller is used in driving a different resonator. In the case of an actuator in a system that has multiple modes characterized by different resonance frequencies, an analog controller can tune erroneously to one of the higher-frequency modes. The lack of programmability of analog controllers is problematic when faults occur, and is especially problematic for preventing tuning to a higher-frequency mode. In contrast, a digital controller can be programmed to restrict itself to a specified frequency range and to maintain stability even when the affected resonator is driven at high power and subjected to uncertain disturbances and variable loads. The present digital control system (see figure) is implemented by means of an algorithm that comprises three main subalgorithms: a hill-climbing control algorithm, an estimation-based extremum-seeking control (ESC) algorithm, and a supervisory algorithm. The hill-climbing algorithm is useful for coarse tracking to find and remain within the vicinity of the resonance. The ESC algorithm is not capable of coarse resonance tracking, but is capable of fine resonance tracking once the estimates of parameters generated by the hill-climbing algorithm have converged sufficiently. On the basis of the parameter-estimation errors, the supervisory algorithm switches operation to whichever of the other two algorithms performs best at a given time.

Aldrich, Jack↗

NASA NTRS2013

NASA Tech Briefs, January 2013

Topics include: Single-Photon-Sensitive HgCdTe Avalanche Photodiode Detector; Surface-Enhanced Raman Scattering Using Silica Whispering-Gallery Mode Resonators; 3D Hail Size Distribution Interpolation/Extrapolation Algorithm; Color-Changing Sensors for Detecting the Presence of Hypergolic Fuels; Artificial Intelligence Software for Assessing Postural Stability; Transformers: Shape-Changing Space Systems Built with Robotic Textiles; Fibrillar Adhesive for Climbing Robots; Using Pre-Melted Phase Change Material to Keep Payloads in Space Warm for Hours without Power; Development of a Centrifugal Technique for the Microbial Bioburden Analysis of Freon (CFC-11); Microwave Sinterator Freeform Additive Construction System (MS-FACS); DSP/FPGA Design for a High-Speed Programmable S-Band Space Transceiver; On-Chip Power-Combining for High-Power Schottky Diode-Based Frequency Multipliers; FPGA Vision Data Architecture; Memory Circuit Fault Simulator; Ultra-Compact Transputer-Based Controller for High-Level, Multi-Axis Coordination; Regolith Advanced Surface Systems Operations Robot Excavator; Magnetically Actuated Seal; Hybrid Electrostatic/Flextensional Mirror for Lightweight, Large-Aperture, and Cryogenic Space Telescopes; System for Contributing and Discovering Derived Mission and Science Data; Remote Viewer for Maritime Robotics Software; Stackfile Database; Reachability Maps for In Situ Operations; JPL Space Telecommunications Radio System Operating Environment; RFI-SIM: RFI Simulation Package; ION Configuration Editor; Dtest Testing Software; IMPaCT - Integration of Missions, Programs, and Core Technologies; Integrated Systems Health Management (ISHM) Toolkit; Wind-Driven Wireless Networked System of Mobile Sensors for Mars Exploration; In Situ Solid Particle Generator; Analysis of the Effects of Streamwise Lift Distribution on Sonic Boom Signature; Rad-Tolerant, Thermally Stable, High-Speed Fiber-Optic Network for Harsh Environments; Towed Subsurface Optical Communications Buoy; High-Collection-Efficiency Fluorescence Detection Cell; Ultra-Compact, Superconducting Spectrometer-on-a-Chip at Submillimeter Wavelengths; UV Resonant Raman Spectrometer with Multi-Line Laser Excitation; Medicine Delivery Device with Integrated Sterilization and Detection; Ionospheric Simulation System for Satellite Observations and Global Assimilative Model Experiments - ISOGAME; Airborne Tomographic Swath Ice Sounding Processing System; flexplan: Mission Planning System for the Lunar Reconnaissance Orbiter; Estimating Torque Imparted on Spacecraft Using Telemetry; PowderSim: Lagrangian Discrete and Mesh-Free Continuum Simulation Code for Cohesive Soils; Multiple-Frame Detection of Subpixel Targets in Thermal Image Sequences; Metric Learning to Enhance Hyperspectral Image Segmentation; Basic Operational Robotics Instructional System; Sheet Membrane Spacesuit Water Membrane Evaporator; Advanced Materials and Manufacturing for Low-Cost, High-Performance Liquid Rocket Combustion Chambers; Motor Qualification for Long-Duration Mars Missions.

Source record↗

DOE OSTI2021

Attacking the IEC-61131 Logic Engine in Programmable Logic Controllers in Industrial Control Systems

In industrial control systems (ICS), programmable logic controllers (PLCs) directly monitor and control a physical process such as nuclear power plants, gas pipelines, and water treatment. They are equipped with a control logic written in IEC-61131 languages (e.g., ladder logic and structured text) that defines how a PLC should control a physical process. A PLC's control logic is a usual target of a cyberattack to sabotage a physical process. For instance, Stuxnet targets a control logic of a Siemens S7-300 PLC to damage a nuclear facility's centrifuges. The existing attacks in the literature generally focus only on injecting malicious control logic into a PLC. This paper presents a new dimension of control logic attacks that target the control logic engine (responsible for running a control logic) of a PLC. It demonstrates that a cyberattack can disable the control logic engine successfully by exploiting inherent PLC features such as program mode and starting/stopping engine. We develop two novel case studies on control logic engine attacks by employing the MITRE ATT\&CK knowledge base on the real-world PLCs used in industry settings, i.e., 1) Schweitzer Engineering Laboratory (SEL)'s Real-Time Automation Controller (SEL-3505 RTAC) equipped with security features such as encrypted traffic and device-level access control, and 2) traditional PLCs, i.e., Schneider Electric's Modicon M221, Allen-Bradley's MicroLogix 1400 and 1100 that do not have security features. The case studies present the internals of the logic engine attacks and facilitate the ICS research community and industry to understand the attack vectors on the control logic engine. We evaluate the effectiveness of the control engine attacks on a power substation, a 4-floor elevator, and a conveyor belt to demonstrate their real-world impact of halting a physical process.

Ali qasim, Syed↗

DOE OSTI2022

Hardware functional obfuscation with ferroelectric active interconnects

Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks.

42 ENGINEERING↗

DOE OSTI2020

An Experimental Feasibility Study on Applying Neutron Tomography to Encapsulated Spent Nuclear Fuel - 20050

Visual inspection makes easier to ensure the integrity and safety of spent nuclear fuel (SNF) than any classical techniques. Various classical techniques have been applied but there are no reliable methods to qualitatively and quantitatively verify spent fuel in dry storage. Thus, the present authors have developed the prototype safeguards apparatus for dry storage employing the array of He-4 gas scintillation detectors (S670E, Arktis Radiation Detectors Ltd., Switzerland), newly designed to simultaneously measure thermal and fast neutrons without any moderators. The S670E detector has a cylindrical shape with a diameter of 52 mm and active length of 600 mm (total length: 875 mm). The detector is filled by He-4 gas with an approximate pressure of 180 bar for fast neutron detection, and its inner wall is coated by Li-6 for thermal neutron detection. The scintillation lights generated via Li-6 nuclear reaction and elastic scattering are collected by 24 SiPMs linearly paired at the center of the detector. The detector delivers a TTL (Transistor-Transistor Logic) output for pulse readout and UART (Universal Asynchronous Receiver Transmitter) for device control. In order to assess feasibility of the apparatus, an experimental system has been designed, built, and optimized via computational studies. Cf-252 neutron sources and linearly arrayed detectors, working as a single detector, were occupied for this study due to the difficulties in working with SNF. The laboratory scale cask (diameter: 0.67 m, height: 1.5 m), minimized by a factor of 10 compared to the actual thickness of a commercial TN-32 cask, was also manufactured. The detector array was designed to rotate the lab-scale cask and obtain 36 image profiles at every 10 degrees. All profiles were aligned in single frame image called a sinogram, and the cross-sectional image was then fabricated by the inverse radon transform algorithm. These experiments have been repeated with different configurations and numbers of sources. Some gamma-ray sources were also measured with neutron sources in order to distinguish between neutron and gamma-ray pulses. Basically, a He-4 detector is designed to run on Linux OS so it is difficult to directly apply to Windows-based equipment widely used in S. Korea. Therefore, a new data acquisition board working on Windows OS was designed and built. The board mainly consists of FPGA (Field Programmable Gate Array) and SoC (System on Chip) for TTL pulse readout, sorting measured data, and transferring data to a user interface. In conclusion, the tomographic system at lab-scale has shown considerable potential to detect a partial or gross defect of encapsulated assemblies in dry storage. Next steps of this study will be to 1) repeatedly carry out experiments to demonstrate scientific reliability and validity, and 2) numerically integrate signals with weight factors to enhance the image quality since the suggested system based on passive interrogation method requires longer measurement time. Finally, the system will apply to a commercial dry storage phased out soon in S. Korea. (authors)

07 ISOTOPE AND RADIATION SOURCES↗

NASA NTRS2006

A Fixed Point VHDL Component Library for a High Efficiency Reconfigurable Radio Design Methodology

Advances in Field Programmable Gate Array (FPGA) technologies enable the implementation of reconfigurable radio systems for both ground and space applications. The development of such systems challenges the current design paradigms and requires more robust design techniques to meet the increased system complexity. Among these techniques is the development of component libraries to reduce design cycle time and to improve design verification, consequently increasing the overall efficiency of the project development process while increasing design success rates and reducing engineering costs. This paper describes the reconfigurable radio component library developed at the Software Defined Radio Applications Research Center (SARC) at Goddard Space Flight Center (GSFC) Microwave and Communications Branch (Code 567). The library is a set of fixed-point VHDL components that link the Digital Signal Processing (DSP) simulation environment with the FPGA design tools. This provides a direct synthesis path based on the latest developments of the VHDL tools as proposed by the BEE VBDL 2004 which allows for the simulation and synthesis of fixed-point math operations while maintaining bit and cycle accuracy. The VHDL Fixed Point Reconfigurable Radio Component library does not require the use of the FPGA vendor specific automatic component generators and provide a generic path from high level DSP simulations implemented in Mathworks Simulink to any FPGA device. The access to the component synthesizable, source code provides full design verification capability:

Hoy, Scott D.↗

DOE OSTI2020

The organic redox transistor for neuromorphic computing

Inspired by the in-memory computing architectures of biological systems, neuromorphic computing using crossbar arrays of artificial synapses based on non-volatile memory (NVM) devices with variable conductances has emerged as a new paradigm to enable massively parallel and ultra-low power computing hardware for data centric applications. Although inference has been demonstrated successfully using crossbars based on a variety of NMV technologies, efficient learning and scaling to large arrays (>10 6 elements) remains a challenge due to the synaptic elements' non-ideal electrical characteristics which degrades ANN accuracy. A further challenge is that in the conductive state memristors draw large currents >μA resulting in significant voltage drops in the interconnect wires and increased probability of failure in scaled arrays. We suggest the organic polymer redox transistor (RT) is an alternate approach that could solve many of these challenges, enabling both inference and parallel outer product updates, as recently demonstrated by Fuller et al. An RT consists of redox-active channel and gate electrodes in contact with a liquid or solid electrolyte. lon insertion through the electrolyte controls the channel electronic conductivity, while electron transfer through an external circuit maintains overall charge neutrality. Unlike a rechargeable battery, in the RT the voltage built-up across the electrolyte is kept to a minimum (typically <100 mV) by using the same material for the gate and channel. Elimination of the voltage offset simplifies integration of the RT into programmable arrays by enabling the use of various selectors. RTs based on inorganic and organic materials have been recently demonstrated with conductance tuning occurring at potentials of just a few mV and hundreds to thousands of linearly and symmetrically programmable conductance states, enabling near ideal accuracy in neural network simulations. Introduced in the 1980's, redox transistors with metallic gate electrodes and organic channel materials, also known as organic electrochemical transistors (OECTs), have been explored for a variety of applications such as chem- and bio-sensing, neural interfaces, and low cost printed circuits. A typical channel material for OECTs is the conducting polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonate) (PEDOT:PSS). PEDOT is a p-type semiconducting polymer with mobile positively charged polarons that hop chain-to-chain.

Talin, Albert Alec↗

DOE OSTI2021

Indoor Occupant Counting by RF Backscattering

Building HVAC (heating, ventilation and air conditioning) consumes approximately 13% of all energy consumption in USA. Motion detectors, cameras and user programmable thermostats have been shown to be ineffective for HVAC controls to save energy, mostly due to the user concerns of comfort, reliability and privacy. A new HVAC control system based on real-time occupant counting that is fully automated, highly accurate, economically sensible and preserving privacy and aesthetics can thus bring forth a disruptive impact to this large energy sector. Our indoor occupant monitoring technology is based on the radio-frequency identification system (RFID), deployed in the room, not on the occupants. One reader with four antennas can be deployed on the ceiling or behind the ceiling panels for every thousand square feet in home, office and assisted living, with or without room partitions. The sticker-like passive tag, 10 cents each and maintenance-free, are profusely hidden on the wall or inside the furniture at arbitrary position, preserving privacy and aesthetics. The large number of tags can realize diverse observation points to accommodate arbitrary room layouts, which is impractical by other active units of camera, infrared, radar or lidar. With 20 tags, the system can reliably detect the number of occupants. For 100 tags, occupant posture and location can be known. The technology has been verified in the research labs and test buildings with very high accuracy. When the real-time occupant number can be accurately known without assuming devices on occupants or occupant motion, the building HVAC system can be automated to achieve building energy saving without sacrificing occupant comfort. According to our limited testing in a few types of building models and the simplified cost calculation, the RFID system has low overall cost in production, deployment, operation and maintenance. The signal processing algorithm based on machine learning requires very small number of training cases as most learning is transferrable for various layouts, and very low computational needs during operation, according to our testing in four different room sizes and layouts. In our preliminary estimate from HVAC saving alone, the RFID system can potentially pay for itself within 1.5 years, in addition to the other enhancement in building automation systems (BAS). Our commercialization strategy and business pitch deck focus on venturing this Cornell occupant monitoring technology into BAS and energy management markets. We have identified three broad BAS market segments of senior living, residential buildings, and office buildings. We have put together the minimum viable product characteristics for these identified segments, including analyses on total cost and competing technologies, as well as the fit and technical gaps for these market segments. We intend to bring the technology to market by licensing or partnering with existing BAS vendors. A list of potential collaborators and licensing partner candidates was assembled for different aspects of integrating our technology into a potential product that can be used with BAS.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

NASA NTRS2010

Smart Power Supply for Battery-Powered Systems

A power supply for battery-powered systems has been designed with an embedded controller that is capable of monitoring and maintaining batteries, charging hardware, while maintaining output power. The power supply is primarily designed for rovers and other remote science and engineering vehicles, but it can be used in any battery alone, or battery and charging source applications. The supply can function autonomously, or can be connected to a host processor through a serial communications link. It can be programmed a priori or on the fly to return current and voltage readings to a host. It has two output power busses: a constant 24-V direct current nominal bus, and a programmable bus for output from approximately 24 up to approximately 50 V. The programmable bus voltage level, and its output power limit, can be changed on the fly as well. The power supply also offers options to reduce the programmable bus to 24 V when the set power limit is reached, limiting output power in the case of a system fault detected in the system. The smart power supply is based on an embedded 8051-type single-chip microcontroller. This choice was made in that a credible progression to flight (radiation hard, high reliability) can be assumed as many 8051 processors or gate arrays capable of accepting 8051-type core presently exist and will continue to do so for some time. To solve the problem of centralized control, this innovation moves an embedded microcontroller to the power supply and assigns it the task of overseeing the operation and charging of the power supply assets. This embedded processor is connected to the application central processor via a serial data link such that the central processor can request updates of various parameters within the supply, such as battery current, bus voltage, remaining power in battery estimations, etc. This supply has a direct connection to the battery bus for common (quiescent) power application. Because components from multiple vendors may have differing power needs, this supply also has a secondary power bus, which can be programmed a priori or on-the-fly to boost the primary battery voltage level from 24 to 50 V to accommodate various loads as they are brought on line. Through voltage and current monitoring, the device can also shield the charging source from overloads, keep it within safe operating modes, and can meter available power to the application and maintain safe operations.

Krasowski, Michael J.↗

DOE OSTI2020

OpenACC unified programming environment for GPU and FPGA multi-hybrid acceleration

Attached accelerators have been frequently used in recent High Per- formance Computing (HPC) systems because of their high performance/power ratio. In particular, the Graphics Processing Unit (GPU) is the most popu- lar accelerator owing to its high peak FLOPS performance and high memory bandwidth supported by HBM2, etc. However, the performance of GPU depends highly on a large degree of SIMD parallelism and has difficulty sustaining a high performance on programs with frequent branch operations or a partially low degree of parallelism.By contrast, a Field Programmable Gate Array (FPGA) has received attention as a different type of accelerator than GPU as a fully reconfigurable processor fitting the target applications. The high performance of FPGA is mainly provided by a pipelined operation and optimized circuit suitable for any operation even with frequent conditional branches. We have been focusing on the flexibility of FPGA to compensate for the weakness of GPU. We believe that the coupling of GPU with FPGA can result in one of the most powerful accelerating platforms available.However, the program coding of GPU and FPGA coupling can be quite difficult for application users. Traditionally, CUDA by NVIDIA has been the most popular programming language with the largest share of GPUs used in HPC, whereas a hardware description language such as Verilog HDL has been used in FPGA programming. OpenCL coding has recently become available even on high-end FPGAs. Moreover, several recent studies have also enabled the OpenACC coding for use in FPGA. In this study, we provide a unified programming system based on OpenACC for a platform equipped with both GPU and FPGA aiming at the next-generation accelerated supercomputer framework. Our programming environment is called Multi-Hybrid OpenACC Translator (MHOAT), and in this paper, we describe the basic concept and prototype system of MHOAT based on an evaluation on the amount of coding required and the performance of a hybrid multi-device accelerated system.

Tsunashima, Ryuta↗

NASA NTRS2012

Hardware Implementation of Lossless Adaptive Compression of Data From a Hyperspectral Imager

Efficient onboard data compression can reduce the data volume from hyperspectral imagers on NASA and DoD spacecraft in order to return as much imagery as possible through constrained downlink channels. Lossless compression is important for signature extraction, object recognition, and feature classification capabilities. To provide onboard data compression, a hardware implementation of a lossless hyperspectral compression algorithm was developed using a field programmable gate array (FPGA). The underlying algorithm is the Fast Lossless (FL) compression algorithm reported in Fast Lossless Compression of Multispectral- Image Data (NPO-42517), NASA Tech Briefs, Vol. 30, No. 8 (August 2006), p. 26 with the modification reported in Lossless, Multi-Spectral Data Comressor for Improved Compression for Pushbroom-Type Instruments (NPO-45473), NASA Tech Briefs, Vol. 32, No. 7 (July 2008) p. 63, which provides improved compression performance for data from pushbroom-type imagers. An FPGA implementation of the unmodified FL algorithm was previously developed and reported in Fast and Adaptive Lossless Onboard Hyperspectral Data Compression System (NPO-46867), NASA Tech Briefs, Vol. 36, No. 5 (May 2012) p. 42. The essence of the FL algorithm is adaptive linear predictive compression using the sign algorithm for filter adaption. The FL compressor achieves a combination of low complexity and compression effectiveness that exceeds that of stateof- the-art techniques currently in use. The modification changes the predictor structure to tolerate differences in sensitivity of different detector elements, as occurs in pushbroom-type imagers, which are suitable for spacecraft use. The FPGA implementation offers a low-cost, flexible solution compared to traditional ASIC (application specific integrated circuit) and can be integrated as an intellectual property (IP) for part of, e.g., a design that manages the instrument interface. The FPGA implementation was benchmarked on the Xilinx Virtex IV LX25 device, and ported to a Xilinx prototype board. The current implementation has a critical path of 29.5 ns, which dictated a clock speed of 33 MHz. The critical path delay is end-to-end measurement between the uncompressed input data and the output compression data stream. The implementation compresses one sample every clock cycle, which results in a speed of 33 Msample/s. The implementation has a rather low device use of the Xilinx Virtex IV LX25, making the total power consumption of the implementation about 1.27 W.

Keymeulen, Didlier↗

NASA NTRS2012

NASA Tech Briefs, January 2012

Contents of this issue are: (1) Energy-Based Tetrahedron Sensor for High-Temperature, High-Pressure Environments (2) Handheld Universal Diagnostic Sensor (3) Large-Area Vacuum Ultraviolet Sensors (4) Fiber Bragg Grating Sensor System for Monitoring Smart Composite Aerospace Structures (5) Health-Enabled Smart Sensor Fusion Technology (6) Extended-Range Passive RFID and Sensor Tags (7) Hybrid Collaborative Learning for Classification and Clustering in Sensor Networks (8) Self-Healing, Inflatable, Rigidizable Shelter (9) Improvements in Cold-Plate Fabrication (10) Technique for Radiometer and Antenna Array Calibration - TRAAC (11) Real-Time Cognitive Computing Architecture for Data Fusion in a Dynamic Environment (12) Programmable Digital Controller (13) Use of CCSDS Packets Over SpaceWire to Control Hardware (14) Key Decision Record Creation and Approval Module (15) Enhanced Graphics for Extended Scale Range (16) Debris Examination Using Ballistic and Radar Integrated Software (17) Data Distribution System (DDS) and Solar Dynamic Observatory Ground Station (SDOGS) (18) Integration Manager (19) Eclipse-Free-Time Assessment Tool for IRIS (20) Automated and Manual Rocket Crater Measurement Software (21) MATLAB Stability and Control Toolbox Trim and Static Stability Module (22) Patched Conic Trajectory Code (23) Ring Image Analyzer (24) SureTrak Probability of Impact Display (25) Implementation of a Non-Metallic Barrier in an Electric Motor (26) Multi-Mission Radioisotope Thermoelectric Generator Heat Exchangers for the Mars Science Laboratory Rover (27) Uniform Dust Distributor for Testing Radiative Emittance of Dust-Coated Surfaces (28) MicroProbe Small Unmanned Aerial System (29) Highly Stable and Active Catalyst for Sabatier Reactions (30) Better Proton-Conducting Polymers for Fuel-Cell Membranes (31) CCD Camera Lens Interface for Real-Time Theodolite Alignment (32) Peregrine 100-km Sounding Rocket Project (33) SOFIA Closed- and Open-Door Aerodynamic Analyses (34) Sonic Thermometer for High-Altitude Balloons (35) Near-Infrared Photon-Counting Camera for High-Sensitivity Observations (36) Integrated Optics Achromatic Nuller for Stellar Interferometry (37) High-Speed Digital Interferometry (38) Ultra-Miniature Lidar Scanner for Launch Range Data Collection (39) Shape and Color Features for Object Recognition Search (40) Explanation Capabilities for Behavior-Based Robot Control (41) A DNA-Inspired Encryption Methodology for Secure, Mobile Ad Hoc Networks (42) Quality Control Method for a Micro-Nano-Channel Microfabricated Device (43) Corner-Cube Retroreflector Instrument for Advanced Lunar Laser Ranging (44) Electrospray Collection of Lunar Dust (45) Fabrication of a Kilopixel Array of Superconducting Microcalorimeters with Microstripline Wiring Spacecraft Attitude Tracking and Maneuver Using Combined Magnetic Actuators (46) Coherent Detector for Near-Angle Scattering and Polarization Characterization of Telescope Mirror Coatings

Source record↗

NASA NTRS2011

Programmable Aperture with MEMS Microshutter Arrays

A microshutter array (MSA) has been developed for use as an aperture array for multi-object selections in James Webb Space Telescope (JWST) technology. Light shields, molybdenum nitride (MoN) coating on shutters, and aluminum/aluminum oxide coatings on interior walls are put on each shutter for light leak prevention, and to enhance optical contrast. Individual shutters are patterned with a torsion flexure that permits shutters to open 90 deg. with a minimized mechanical stress concentration. The shutters are actuated magnetically, latched, and addressed electrostatically. Also, micromechanical features are tailored onto individual shutters to prevent stiction. An individual shutter consists of a torsion hinge, a shutter blade, a front electrode that is coated on the shutter blade, a backside electrode that is coated on the interior walls, and a magnetic cobalt-iron coating. The magnetic coating is patterned into stripes on microshutters so that shutters can respond to an external magnetic field for the magnetic actuation. A set of column electrodes is placed on top of shutters, and a set of row electrodes on sidewalls is underneath the shutters so that they can be electrostatically latched open. A linear permanent magnet is aligned with the shutter rows and is positioned above a flipped upside-down array, and sweeps across the array in a direction parallel to shutter columns. As the magnet sweeps across the array, sequential rows of shutters are rotated from their natural horizontal orientation to a vertical open position, where they approach vertical electrodes on the sidewalls. When the electrodes are biased with a sufficient electrostatic force to overcome the mechanical restoring force of torsion bars, shutters remain latched to vertical electrodes in their open state. When the bias is removed, or is insufficient, the shutters return to their horizontal, closed positions. To release a shutter, both the electrode on the shutter and the one on the back wall where the shutter sits are grounded. The shutters with one or both ungrounded electrodes are held open. Sub-micron bumps underneath light shields and silicon ribs on back walls are the two features to prevent stiction. These features ensure that the microshutter array functions properly in mechanical motions. The MSA technology can be used primarily in multi-object imaging and spectroscopy, photomask generation, light switches, and in the stepper equipment used to make integrated circuits and MEMS (microelectromechanical systems) devices.

Moseley, Samuel↗

DOE OSTI2024

A prototype scintillator real‐time beam monitor for ultra‐high dose rate radiotherapy

Background: FLASH Radiotherapy (RT) is an emergent cancer RT modality where an entire therapeutic dose is delivered at more than 1000 times higher dose rate than conventional RT. For clinical trials to be conducted safely, a precise and fast beam monitor that can generate out-of-tolerance beam interrupts is required. This paper describes the overall concept and provides results from a prototype ultra-fast, scintillator-based beam monitor for both proton and electron beam FLASH applications. Purpose: A FLASH Beam Scintillator Monitor (FBSM) is being developed that employs a novel proprietary scintillator material. The FBSM has capabilities that conventional RT detector technologies are unable to simultaneously provide: (1) large area coverage; (2) a low mass profile; (3) a linear response over a broad dynamic range; (4) radiation hardness; (5) real-time analysis to provide an IEC-compliant fast beam-interrupt signal based on true two-dimensional beam imaging, radiation dosimetry and excellent spatial resolution. Methods: The FBSM uses a proprietary low mass, less than 0.5 mm water equivalent, non-hygroscopic, radiation tolerant scintillator material (designated HM: hybrid material) that is viewed by high frame rate CMOS cameras. Folded optics using mirrors enable a thin monitor profile of ∼10 cm. A field programmable gate array (FPGA) data acquisition system generates real-time analysis on a time scale appropriate to the FLASH RT beam modality: 100–1000 Hz for pulsed electrons and 10–20 kHz for quasi-continuous scanning proton pencil beams. An ion beam monitor served as the initial development platform for this work and was tested in low energy heavy-ion beams ( 86 Kr +26 and protons). A prototype FBSM was fabricated and then tested in various radiation beams that included FLASH level dose per pulse electron beams, and a hospital RT clinic with electron beams. Results: Results presented in this report include image quality, response linearity, radiation hardness, spatial resolution, and real-time data processing. Furthermore, the HM scintillator was found to be highly radiation damage resistant. It exhibited a small 0.025%/kGy signal decrease from a 216 kGy cumulative dose resulting from continuous exposure for 15 min at a FLASH compatible dose rate of 237 Gy/s. Measurements of the signal amplitude versus beam fluence demonstrate linear response of the FBSM at FLASH compatible dose rates of >40 Gy/s. Comparison with commercial Gafchromic film indicates that the FBSM produces a high resolution 2D beam image and can reproduce a nearly identical beam profile, including primary beam tails. The spatial resolution was measured at 35–40 µm. Tests of the firmware beta version show successful operation at 20 000 Hz frame rate or 50 µs/frame, where the real-time analysis of the beam parameters is achieved in less than 1 µs. Conclusions: The FBSM is designed to provide real-time beam profile monitoring over a large active area without significantly degrading the beam quality. A prototype device has been staged in particle beams at currents of single particles up to FLASH level dose rates, using both continuous ion beams and pulsed electron beams. Using a novel scintillator, beam profiling has been demonstrated for currents extending from single particles to 10 nA currents. Radiation damage is minimal and even under FLASH conditions would require ≥50 kGy of accumulated exposure in a single spot to result in a 1% decrease in signal output. Beam imaging is comparable to radiochromic films, and provides immediate images without hours of processing. Real-time data processing, taking less than 50 µs (combined data transfer and analysis times), has been implemented in firmware for 20 kHz frame rates for continuous proton beams.

2D beam imaging↗

NASA NTRS2004

Event-Driven Random-Access-Windowing CCD Imaging System

A charge-coupled-device (CCD) based high-speed imaging system, called a realtime, event-driven (RARE) camera, is undergoing development. This camera is capable of readout from multiple subwindows [also known as regions of interest (ROIs)] within the CCD field of view. Both the sizes and the locations of the ROIs can be controlled in real time and can be changed at the camera frame rate. The predecessor of this camera was described in High-Frame-Rate CCD Camera Having Subwindow Capability (NPO- 30564) NASA Tech Briefs, Vol. 26, No. 12 (December 2002), page 26. The architecture of the prior camera requires tight coupling between camera control logic and an external host computer that provides commands for camera operation and processes pixels from the camera. This tight coupling limits the attainable frame rate and functionality of the camera. The design of the present camera loosens this coupling to increase the achievable frame rate and functionality. From a host computer perspective, the readout operation in the prior camera was defined on a per-line basis; in this camera, it is defined on a per-ROI basis. In addition, the camera includes internal timing circuitry. This combination of features enables real-time, event-driven operation for adaptive control of the camera. Hence, this camera is well suited for applications requiring autonomous control of multiple ROIs to track multiple targets moving throughout the CCD field of view. Additionally, by eliminating the need for control intervention by the host computer during the pixel readout, the present design reduces ROI-readout times to attain higher frame rates. This camera (see figure) includes an imager card consisting of a commercial CCD imager and two signal-processor chips. The imager card converts transistor/ transistor-logic (TTL)-level signals from a field programmable gate array (FPGA) controller card. These signals are transmitted to the imager card via a low-voltage differential signaling (LVDS) cable assembly. The FPGA controller card is connected to the host computer via a standard peripheral component interface (PCI).

Monacos, Steve↗