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At least 523 records · Page 29

pyRMG: A framework for high-throughput, large-cell DFT calculations on supercomputers

Exascale computing delivers the raw power to simulate ever larger and more chemically realistic systems, but realizing this potential requires codes that can efficiently use thousands of processors. Our real-space multigrid (RMG) density functional theory (DFT) code’s grid-decomposition approach scales nearly linearly with the number of graphics processing units (GPUs), even for simulations exceeding thousands of atoms. This scalability makes RMG a compelling tool for high-throughput DFT studies of materials that would otherwise be bottlenecked in other codes (for example, by global fast Fourier transforms in plane-wave DFT). However, the limited workflow infrastructure for RMG has thus far constrained its adoption to a small user community. In this work, we present pyRMG, a Python package designed to streamline the setup and execution of RMG DFT calculations. Built on the pymatgen and ASE (Atomic Simulation Environment) computational materials science Python packages, pyRMG automates input generation and convergence checking, and it integrates with modern job schedulers (e.g., Flux) on leadership-class platforms such as Frontier and Perlmutter. Here, we demonstrate pyRMG for a high-throughput study of strain effects in 2D 2L-Bi 2 Se 3 /2L-NbSe 2 heterostructures, which offers chemical insights into this system and shows that RMG-based workflows can converge with limited user intervention.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Analog-to-digital converter based on voltage-controlled superconducting devices

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.

Analog-to-digital converter↗

Trapping and detection of single rubidium atoms in an optical dipole trap using a long-focus objective lens

The trapping of single atoms in optical dipole traps is widely used in experiments on the implementation of quantum processors based on neutral atoms, and studying interatomic interactions. Typically, such experiments employ lenses with a large numerical aperture (NA > 0.5), highly sensitive EMCCD cameras, or photon counters. In this work, we demonstrate trapping and detection of single rubidium atoms using a long-focus objective lens with a numerical aperture NA = 0.172 and a FLir Tau CNV sCMOS camera. (paper)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

New developments in structure-property and amorphous materials research at the upgraded 16-BM-B Paris-Edinburgh press station at HPCAT

Beamline 16-BM-B of the High-Pressure Collaborative Access Team (HPCAT) at the Advanced Photon Source (APS) provides a Paris-Edinburgh press program to probe the structure and properties of crystalline and amorphous materials up to 12 GPa at room temperature or 7 GPa at 2000°C. During the recent APS upgrade, 16-BM-B undertook major improvements to its instrumentation and measurement techniques. The upgrade includes the addition of a 1.2 m horizontal “condenser” mirror and a new variable-sized collimation system, the combination of which decreases the acquisition time for energy dispersive X-ray diffraction measurements by a factor of 10 when compared to pre-upgrade measurements. The addition of a new Ge energy-sensitive detector and DANTE (XGLab) digital pulse processor allows for processing the increased diffraction counts with minimal deadtime. In addition to upgraded beamline components, new techniques are being developed for eventual release to the user community, including electrical resistivity and tomography measurements.

APS upgrade↗

Rapid organic carbon spiraling in a headwater stream linked with streamflow, biogeochemistry, and canopy phenology

Headwater streams are abundant worldwide and important to global biogeochemical cycles, serving as critical processors and transporters of C. C spiraling is a useful way to understand the retention and mineralization of organic C (OC) in streams. However, analyses of seasonal and interannual variability in OC spiraling are currently limited. In this study, we aimed to understand the temporal patterns and driving mechanisms of OC spiraling, which will inform our understanding of future OC changes under climate change. We used 7 y of daily data in a small headwater stream (Walker Branch, Tennessee, USA) to assess seasonal and interannual variability in OC spiraling length (S OC ) and mineralization velocity (v fOC ), as well as their potential related variables. On average, S OC in Walker Branch was ~10× shorter than in previously studied small streams, indicating strong connections between the water column and the benthic environment where OC mineralization mostly takes place. OC spiraling was faster during the more biologically active periods of spring and autumn compared with more elongated OC spiraling in summer and winter, when OC retention was lower and downstream transport was higher. Gross primary production (GPP) was most strongly related to S OC and v fOC . Photosynthetically active radiation (PAR) and NO 3 − were also positively and negatively related to v fOC , respectively. Trends toward earlier and longer canopy cover and reduced GPP and PAR may result in longer S OC and slower v fOC , reducing localized instream processing of OC and potentially shunting more OC downstream. However, long-term observations indicate reduced NO 3 − at Walker Branch, suggesting opposing effects to those of GPP and PAR, leading to faster v fOC and greater OC retention. Time-series analyses of OC spiraling in streams can enhance our understanding of current and future responses of OC processing and downstream transport to climate change, as well as implications for downstream OC dynamics.

biological activity↗

An autoencoder compression approach for accelerating large-scale inverse problems

Abstract Partial differential equation (PDE)-constrained inverse problems are some of the most challenging and computationally demanding problems in computational science today. Fine meshes required to accurately compute the PDE solution introduce an enormous number of parameters and require large-scale computing resources such as more processors and more memory to solve such systems in a reasonable time. For inverse problems constrained by time-dependent PDEs, the adjoint method often employed to compute gradients and higher order derivatives efficiently requires solving a time-reversed, so-called adjoint PDE that depends on the forward PDE solution at each timestep. This necessitates the storage of a high-dimensional forward solution vector at every timestep. Such a procedure quickly exhausts the available memory resources. Several approaches that trade additional computation for reduced memory footprint have been proposed to mitigate the memory bottleneck, including checkpointing and compression strategies. In this work, we propose a close-to-ideal scalable compression approach using autoencoders to eliminate the need for checkpointing and substantial memory storage, thereby reducing the time-to-solution and memory requirements. We compare our approach with checkpointing and an off-the-shelf compression approach on an earth-scale ill-posed seismic inverse problem. The results verify the expected close-to-ideal speedup for the gradient and Hessian-vector product using the proposed autoencoder compression approach. To highlight the usefulness of the proposed approach, we combine the autoencoder compression with the data-informed active subspace (DIAS) prior showing how the DIAS method can be affordably extended to large-scale problems without the need for checkpointing and large memory.

Mathematics↗

3D simulations of inertial confinement fusion implosions part 1: inline modeling of polarized cross beam energy transfer and subsequent drive anomalies on OMEGA and NIF

Inertial confinement fusion experiments are sensitive to cross-beam energy transfer (CBET), a laser-plasma instability that redistributes laser energy in the coronal plasma through self-generated ion acoustic wave (IAW) gratings. The detailed CBET coupling depends on the polarization state of the crossing wavefields. CBET itself can also scramble the beam polarizations by inducing ellipticity through the IAW grating, and rotating the seed polarization toward that of the pump. We develop a ray-based model that describes the polarized CBET coupling and that is compatible with the framework of 3D inline radiative hydrodynamics simulations. The model is implemented in the ASTER/IFRIIT code and verified against an academic test case and an offline polarized CBET post-processor. It is then applied to the detailed configuration of the distributed polarization rotator system on OMEGA, where results highlight how polarized CBET induces significant low modes in the collisional absorption source term. Finally, the modeling is applied to a simple indirect-drive configuration, comparing CBET calculations with 96 unpolarized or polarized beams with 24 unpolarized quads. It is shown that these cases produce similar power amplification per cone of beams grouped with similar polar angles. However, the 96 beam geometry itself is found to reduce azimuthal variations in quad power after the interaction and favors beams with larger polar angles within the cones, an effect that is amplified by the polarized CBET. Application of the model to inline calculations of OMEGA implosions are presented in a companion paper.

3D inline modeling↗

Dynamic mode decomposition for gyrokinetic eigenmode analysis

Dynamic mode decomposition (DMD) is a post-processing approach to decompose a complex time series into a set of modes via spectral analysis. DMD provides a new and powerful method to recover gyrokinetic drift-wave eigenfrequencies and eigenfunctions based only on the solution of the gyrokinetic-Maxwell initial value problem with almost no added cost to the initial value solver. In the present paper, DMD is applied to the CGYRO gyrokinetic code using a newly-developed CGYRO-DMD post-processor. CGYRO-DMD is numerically efficient, even on a single CPU. It does not set any restrictions on the plasma shape, beta (ratio of the plasma pressure to the magnetic field pressure), collisionality or number of species, and allows one to resolve numerous eigenmodes, even of comparable growth rates. In addition, DMD is not limited to unstable modes, but rather can capture stable and unstable branches simultaneously. In this work, we illustrate the accuracy of DMD through gyrokinetic analysis of mode transition for electromagnetic drift wave instabilities.

drift-wave eigenmodes↗

Full configuration interaction simulations of exchange-coupled donors in silicon using multi-valley effective mass theory

Abstract Donor spins in silicon have achieved record values of coherence times and single-qubit gate fidelities. The next stage of development involves demonstrating high-fidelity two-qubit logic gates, where the most natural coupling is the exchange interaction. To aid the efficient design of scalable donor-based quantum processors, we model the two-electron wave function using a full configuration interaction method within a multi-valley effective mass theory. We exploit the high computational efficiency of our code to investigate the exchange interaction, valley population, and electron densities for two phosphorus donors in a wide range of lattice positions, orientations, and as a function of applied electric fields. The outcomes are visualized with interactive images where donor positions can be swept while watching the valley and orbital components evolve accordingly. Our results provide a physically intuitive and quantitatively accurate understanding of the placement and tuning criteria necessary to achieve high-fidelity two-qubit gates with donors in silicon.

Joecker, Benjamin (ORCID:0000000302635440)↗

Quantum utility-scale error mitigation for quantum quench dynamics in Heisenberg spin chains

Here, we implement a quantum error mitigation method termed self-mitigation, which is comparable to zero-noise extrapolation, at large scales to achieve quantum utility on near-term, noisy quantum computers. We investigate the effectiveness of several quantum error mitigation strategies, including self-mitigation, by simulating quantum quench dynamics for Heisenberg spin chains with system sizes up to 104 qubits using IBM quantum processors. In particular, we discuss the limitations of zero-noise extrapolation and the advantages offered by self-mitigation at large scales. The self-mitigation method demonstrates stable accuracy with large systems of 104 qubits comprising more than 3,000 CNOT gates. Also, we combine the discussed quantum error mitigation methods with practical entanglement entropy measuring methods, and it shows a good agreement with the theoretical estimation. Our study illustrates the usefulness of near-term noisy quantum hardware in examining the quantum quench dynamics of many-body systems at large scales and lays the groundwork for surpassing classical simulations with quantum methods prior to the development of fault-tolerant quantum computers.

97 MATHEMATICS AND COMPUTING↗

Preliminary design overview and performance assessment of the ITER low-field side reflectometer

The design of the ITER low-field side reflectometer (LFSR) has matured to a complete end-to-end preliminary design. LFSR will supply three key plasma measurements: (1) electron density profile, (2) electron density fluctuations, and (3) poloidal rotation. Simultaneous measurements of the three quantities are enabled by an array of six monostatic antennas which inject from an equatorial port on the outboard side of the ITER vessel. Low-loss transmission lines, consisting of corrugated, overmoded waveguide and miter bends, transmit the 30–165 GHz, O- and X-mode signals to and from the ITER plasma. Integrated transmission-line components serve a range of purposes, such as protection from high-power stray radiofrequency radiation, accommodation of transmission-line displacement, and simultaneous measurement of reference and plasma phases during the discharge. Broadband transmission signals are realized by full-band microwave transceivers combined with quasi-optical multiplexing. A field-programmable gate array (FPGA) processor demodulates the profile reflectometer signals, enabling real-time density profile measurements for plasma control system feedback. A full-scale transmission line test facility provides an integrated environment to assess the performance of critical LFSR components. Theoretical modeling together with insertion loss measurements provide the basis for a comprehensive power budget, which accounts for transmitted output power, transmission-line losses, antenna coupling, and plasma effects. Results indicate that high signal-to-noise ratios are achievable with the current design. A synthetic reflectometer model, using real design parameters and baseline ITER profiles, has been developed to estimate the return signal. With evolving microwave and data acquisition technologies, full-band, ultrafast sweeps (<1 μs) will be realizable for ITER.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

Production and tests of the ADDC for the Micromegas detector of the ATLAS New Small Wheel

The Large Hadron Collider (LHC) at CERN will perform a series of upgrades to allow luminosity increases during the next physics runs expected from 2022 on. These will also significantly increase the trigger rates of all the detectors. As part of the ATLAS Phase-I upgrade, the current Small Wheel muon detectors will be replaced with state-of-the-art New Small Wheel (NSW) detectors to cope with the increased luminosity of the LHC. The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data from the resistive Micro-Mesh Gaseous Structure (Micromegas) detectors of the NSW. The ART ASIC on the ADDC is a customdesigned chip to receive theAddress in Real Time (ART) signals from theVMMfront-end ASIC and perform hit-selection processing. The processed trigger data is then sent to the Trigger Processor (TP) through optical links. A total of 512 ADDCs will be installed on the detector close to the front-end boards. Therefore, those cards must be able to work properly in a high radiation and magnetic field environment. Furthermore, after four rounds of prototyping, the ADDC production was launched in January of 2019. 600 ADDC boards have been produced and tested with an automated test stand. This test setup can simulate the front-end signals and provide "Level-1 Data Driver Card" (L1DDC) functions as well as part of the TP functions. Thus, the ADDC functionality and stability can be verified without the remaining NSW electronics. This paper describes the ADDC hardware prototype development, radiation and integration testing, and the ADDC automated production test procedure.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

Prototype hardware design and testing of the global common module for the global trigger subsystem of the ATLAS phase-II upgrade

We report the High-Luminosity Large Hadron Collider (HL-LHC) will deliver more than ten times the integrated luminosity of the previous runs combined. Meeting its stricter throughput requirements poses new challenges to the Trigger and Data Acquisition (TDAQ) systems of the LHC experiments. Introduced in the framework of the ATLAS experiment’s HL upgrade, the Global Trigger (GT) is a new subsystem which will perform offline-like algorithms on full-granularity calorimeter data. The implementation of the GT’s functionality is firmware-focused and is composed of three layers: multiplexing (or data aggregating), global event processing, and demultiplexing interface to the central trigger processor. Each layer will be composed of several, similar nodes, hosted on replicas of identical hardware, the Global Common Module (GCM), an ATCA front board which is designed to be adopted throughout the entire GT subsystem. This article proceeds from the TWEPP 2021 conference and presents the GCM hardware design, performed in 2020, and focuses on some key results of its extensive testing performed in 2021.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Nanosecond machine learning regression with deep boosted decision trees in FPGA for high energy physics

We present a novel application of the machine learning / artificial intelligence method called boosted decision trees to estimate physical quantities on field programmable gate arrays (FPGA). The software package fwXmachina features a new architecture called parallel decision paths that allows for deep decision trees with arbitrary number of input variables. It also features a new optimization scheme to use different numbers of bits for each input variable, which produces optimal physics results and ultraefficient FPGA resource utilization. Problems in high energy physics of proton collisions at the Large Hadron Collider (LHC) are considered. Estimation of missing transverse momentum (E T miss ) at the first level trigger system at the High Luminosity LHC (HL-LHC) experiments, with a simplified detector modeled by Delphes, is used to benchmark and characterize the firmware performance. The firmware implementation with a maximum depth of up to 10 using eight input variables of 16-bit precision gives a latency value of $\mathcal{O}$(10) ns, independent of the clock speed, and $\mathcal{O}$(0.1)% of the available FPGA resources without using digital signal processors.

Instruments & Instrumentation↗

Hardware design and testing of the generic rear transition module for the global trigger subsystem of ATLAS Phase-II Upgrade

Abstract In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 μs-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, made up of an Advanced Telecommunications Computing Architecture (ATCA) front board, called Global Common Module (GCM), and a rear transition module (RTM), called Generic RTM (GRM). The GRM, which was developed to mitigate the risks deriving from the complex design and power management of the GCM, features an advanced Xilinx Versal Prime system-on-chip and can handle communication with the GCM and Front-End Link eXchange (FELIX) subsystem and trigger processors through 124 25.8 Gb/s transceiver links, for readout and control. Additionally, the GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This paper presents the GRM hardware design and its testing.

Instruments & Instrumentation↗

The New Small Wheel electronics

The increase in luminosity, and consequent higher backgrounds, of the LHC upgrades require improved rejection of fake tracks in the forward region of the ATLAS Muon Spectrometer. The New Small Wheel upgrade of the Muon Spectrometer aims to reduce the large background of fake triggers from track segments that don't originate from the interaction point. The New Small Wheel employs two detector technologies, the resistive strip Micromegas detectors and the “small” Thin Gap Chambers, with a total of 2.45 million electrodes to be sensed. The two technologies require the design of a complex electronics system given that it consists of two different detector technologies and is required to provide both precision readout and a fast trigger. It will operate in a high background radiation region up to about 20 kHz/cm 2 at the expected HL-LHC luminosity of $\mathcal{L}$= 7.5 × 10 34 cm -2 s -1 . The architecture of the system is strongly defined by the GBTx data aggregation ASIC, the newly-introduced FELIX data router and the software based data handler of the ATLAS detector. The electronics complex of this new detector was designed and developed in the last ten years and consists of multiple radiation tolerant Application Specific Integrated Circuits, multiple front-end boards, dense boards with FPGA's and purpose-built Trigger Processor boards within the ATCA standard. The New Small Wheel has been installed in 2021 and is undergoing integration within ATLAS for LHC Run 3. It should operate through the end of Run 4 (December 2032). In this manuscript, the overall design of the New Small Wheel electronics is presented.

47 OTHER INSTRUMENTATION↗

The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results

Exploiting the “sparse” nature of the information in XPCS (X-ray Photon Correlation Spectroscopy) and XSVS (Speckle Visibility Spectroscopy) experiments, we present the SparkPix-S, a 3-sides buttable Application Specific Integrated Circuit (ASIC) based on a sparsified readout strategy for large-format hybrid detectors. The SparkPix-S architecture, based on the successful ePix family, will be composed as follows: a front-end 2-D matrix of 384×352 square pixels with 50 µm pitch is arranged to match the dimensions of a PIN Si-sensor matrix; charge readout, signal shaping and amplitude discrimination is performed at pixel-level, by means of a low-power (<18 µW) analog processor, which, in case of an event, negotiates access to an analog bus placed every other column; on the chip periphery (balcony), the information on each bus is digitized by an array of successive approximation analog-to-digital converters (SAR-ADCs) running at 10 Msps; on the digital back-end the global logic will generate the output data stream using low-voltage differential signalling (LVDS). A first prototype of the SparkPix-S, with a reduced matrix size of 96×96 pixels, is currently under production on a 130 nm CMOS technology. Simulated performance results show an equivalent noise charge <60 el. r.m.s. at 1 MHz repetition rate, with a maximum input energy of 60 keV and capability to discriminate charge signals with equivalent energy as low as 900 eV.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

SALSA: a new versatile readout chip for MPGD detectors

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other usages of MPGD detectors like TPC or photon detectors. It integrates a frontend block and an ADC for each of the 64 channels, associated to a configurable DSP processor meant to correct data and reduce the raw data flux to limit the output bandwidth. It will be compatible with the continuous readout foreseen for the EPIC DAQ, but will also work in a triggered environment. Several prototypes are already produced in order to qualify the different blocks of the chip, in particular the frontend, the ADC and the clock generation. The next 32-channel prototype is currently under development and is planed to be produced in 2025. In conclusion, the final prototype will be produced and tested from 2026 for a production of the SALSA chip at the horizon of 2027.

Data processing↗