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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 523 records · Page 29
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

EmSense: A High-Resolution Emulated Sensor for Experiments with the Smart Grid and Distributed Ledger Technology

This work involves the development of a device - EmSense (“Emulated Sensor”) - that emulates a high-resolution sensor for a power grid. The device collects raw current and voltage sensor data which derive from ORNL's signature library. This library is a dataset that ORNL curates from many different sources that include power systems from various utilities. The EmSense packages the data from the library in the form of IEC 61850 Sampled Value (SV) packets and then broadcasts these SV packets on the network. In another mode, EmSense can generate artificial sinusoidal data that appears as waveforms for voltage and current signals. EmSense has an internal algorithm for determining the period of a signal based on the data so that the period can be specified as a variable in the IEC 61850 packets. The purpose of EmSense is to allow for experimentation with the Dark Net Infrastructure where a variety of power line sensors must be represented along with their typical communication traffic. The EmSense device was developed in coordination with the software for receiving and processing the packets in the Distributed Ledger Technology (DLT) framework of the DarkNet Project. This receiving software must have a methodology for dealing with information of high velocity, variety, and volume. Experimenting with EmSense facilitates the development of such software. The results showed that the DLT framework and the trust-anchoring approach managed to process a large flow of traffic even with up to six instances of EmSense device broadcasting data. This was achieved without overfilling packet queues in the memory of the actual hardware of the DLT devices or causing the Central Processing Unit (CPU) of the hardware to be overwhelmed. The DLTs were also able to store the data in a compact and useful form for later analysis and archival purposes.

Werth, Aaron↗
NASA NTRS1979

Implementing a bubble memory hierarchy system

This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

Segura, R.↗
NASA NTRS1987

Gigarad-tolerant power switches and memory elements

A new class of silicon devices operating without p-n junctions has been studied for radiation hardness. The electric field in these devices is uniform over most of the device, thus causing high-voltage breakdown to increase with electrode spacing. Deep acceptor levels are created in the silicon by diffusing gold atoms into the lattice, or by electron radiation. These acceptor levels, near the center of the band gap, trap out electrons so that the low resistivity of the n-type doped wafer can be raised to intrinsic resistivity. Switching between a high-resistivity state at low currents and a low-resistivity state at high currents occurs at a definite threshold voltage, exhibiting characteristics similar to silicon-controlled rectifiers. Compensating 0.1 ohm-meter (10 ohm-cm) silicon wafers requires electron fluxes of 10 to the 23rd electrons per square meter (10 to the 19th electrons per square centimeter). Experiments demonstrating gamma tolerance to 1 Gigarad(Si) are described. Calculations for maximum tolerable neutron fluence are shown, and a phenomenological explanation for these results is presented.

Joyner, W. T.↗
DOE OSTI2021

Recent developments on 2D magnetic materials: challenges and opportunities

The emergence of two-dimensional (2D) magnetic materials exhibiting strong magnetization at ultrathin limits above room temperature are promising for miniaturization of devices beyond Moore’s law for future energy efficient nano-electronic devices. Here, the current status, different mechanisms for the existence of magnetism, spin current injection and other magnetic properties of monolayer to few-layers of various 2D magnetic materials are reviewed. Some of the promising applications of these materials are spintronics devices such as spin valves, spin tunnel field-effect transistors, and spin filtering magnetic tunnel junctions. Due to the tunable electronic properties of these 2D materials, it's quite interesting to inject the spin current with suitable ferromagnetic contacts. For instance,black phosphorus is a layered material with a small Schottky barrier height capable of injecting spin current. This review includes many recently explored 2D magnetic materials ranging from exfoliated 2D crystals to CVD grown materials from single to several layers, demonstrating tunable layer dependent magnetic properties. We also explore some of the promising theoretical study based on 2D magnetic compounds such as 2D alkali-based chromium chalcogenides, which shows ferromagnetic as well as semiconducting behavior. The layer-dependent magnetic ordering has been observed in layered compounds like 1T-CrTe 2 , VSe 2 , CrI 3 , and Fe 3 GeTe 2 , which have great potential for the future applications in magnetic based electronic devices. Finally, we emphasize the challenges, opportunities and future directions of the 2D magnetic materials, where new discoveries might have outstanding impact in transformational scientific breakthroughs towards memory, spintronics, optoelectronics and other multifunctional device applications.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Variation-Resilient FeFET-Based In-Memory Computing Leveraging Probabilistic Deep Learning

Reliability issues stemming from device level nonidealities of nonvolatile emerging technologies like ferroelectric field-effect transistors (FeFETs), especially at scaled dimensions, cause substantial degradation in the accuracy of in-memory crossbar-based AI systems. Here, in this work, we present a variation-aware design technique to characterize the device level variations and to mitigate their impact on hardware accuracy employing a Bayesian neural network (BNN) approach. An effective conductance variation model is derived from the experimental measurements of cycle-to-cycle (C2C) and device-to-device (D2D) variations performed on FeFET devices fabricated using 28 nm high-k metal gate technology. The variations were found to be a function of different conductance states within the given programming range, which sharply contrasts earlier efforts where a fixed variation dispersion was considered for all conductance values. Such variation characteristics formulated for three different device sizes at different read voltages were provided as prior variation information to the BNN to yield a more exact and reliable inference. Near-ideal accuracy for shallow networks (MLP5 and LeNet models) on the MNIST dataset and limited accuracy decline by ~3.8%–16.1% for deeper AlexNet models on CIFAR10 dataset under a wide range of variations corresponding to different device sizes and read voltages, demonstrates the efficacy of our proposed device-algorithm co-design technique.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Unconventional unidirectional magnetoresistance in heterostructures of a topological semimetal and a ferromagnet

Unidirectional magnetoresistance (UMR) in a bilayer heterostructure, consisting of a spin-source material and a magnetic layer, refers to a change in the longitudinal resistance on the reversal of magnetization and originates from the interaction of non-equilibrium spin accumulation and magnetization at the interface. Since the spin polarization of an electric-field-induced non-equilibrium spin accumulation in conventional spin-source materials is restricted to be in the film plane, the ensuing UMR can only respond to the in-plane component of magnetization. However, magnets with perpendicular magnetic anisotropy are highly desired for magnetic memory and spin-logic devices, whereas the electrical read-out of perpendicular magnetic anisotropy magnets through UMR is critically missing. Here, in this study, we report the discovery of an unconventional UMR in the heterostructures of a topological semimetal (WTe 2 ) and a perpendicular magnetic anisotropy ferromagnetic insulator (Cr 2 Ge 2 Te 6 ), which allows to electrically read the up and down magnetic states of the Cr 2 Ge 2 Te 6 layer through longitudinal resistance measurements.

Kao, I-Hsuan [Carnegie Mellon Univ., Pittsburgh, P↗
DOE OSTI2020

Empowering 2D nanoelectronics via ferroelectricity

Introducing ferroelectricity to two-dimensional (2D) van der Waals (vdW) materials such as graphene, transition metal dichalcogenides, and black phosphorous presents a promising route for developing high-speed and low-power nanoelectronics. This Perspective reviews two actively pursued materials strategies, ferroelectric/vdW heterostructures and vdW ferroelectric materials. Finally, the topics discussed include their application potential and performance limitations as memory, logic, sensing, and optical devices, as well as the challenges and outlook of the field.

2D materials↗
DOE OSTI2021

Colloquium : Physical properties of group-IV monochalcogenide monolayers

The state-of-the-art knowledge of ferroelectric and ferroelastic group-IV monochalcogenide monolayers is surveyed. These semiconductors feature remarkable structural and mechanical properties, such as a switchable in-plane spontaneous polarization, soft elastic constants, structural degeneracies, and thermally driven two-dimensional structural transformations. Additionally, these 2D materials display selective valley excitations, valley Hall effects, and persistent spin helix behavior. After a description of their Raman spectra, a discussion of optical properties arising from their lack of centrosymmetry (such as an unusually strong second-harmonic intensity, large bulk photovoltaic effects, photostriction, and tunable exciton binding energies) is provided as well. Here, the physical properties observed in these materials originate from (correlate with) their intrinsic and switchable electric polarization, and the physical behavior hereby reviewed could be of use in nonvolatile memory, valleytronic, spintronic, and optoelectronic devices: these 2D multiferroics enrich and diversify the 2D material toolbox.

2D ferroelectrics↗
DOE OSTI2023

Revisiting Temporal Blocking Stencil Optimizations

Iterative stencils are used widely across the spectrum of High Performance Computing (HPC) applications. Many efforts have been put into optimizing stencil GPU kernels, given the prevalence of GPU-accelerated supercomputers. To improve the data locality, temporal blocking is an optimization that combines a batch of time steps to process them together. Under the observation that GPUs are evolving to resemble CPUs in some aspects, we revisit temporal blocking optimizations for GPUs. We explore how temporal blocking schemes can be adapted to the new features in the recent Nvidia GPUs, including large scratchpad memory, hardware prefetching, and device-wide synchronization. We propose a novel temporal blocking method, EBISU, which champions low device occupancy to drive aggressive deep temporal blocking on large tiles that are executed tile-by-tile. We compare EBISU with state-of-the-art temporal blocking libraries: STENCILGEN and AN5D. We also compare with state-of-the-art stencil auto-tuning tools that are equipped with temporal blocking optimizations: ARTEMIS and DRSTENCIL. Over a wide range of stencil benchmarks, EBISU achieves speedups up to 2.53x and a geometric mean speedup of 1.49x over the best state-of-the-art performance in each stencil benchmark.

Zhang, Lingqi↗
DOE OSTI2024

Strain-concentration for fast, compact photonic modulation and non-volatile memory

A critical figure of merit (FoM) for electro-optic (EO) modulators is the transmission change per voltage, d T / d V . Conventional approaches in wave-guided modulators maximize d T / d V via a high EO coefficient or longer light-material interaction lengths but are ultimately limited by material losses and nonlinearities. Optical and RF resonances improve d T / d V at the cost of spectral non-uniformity, especially for high- Q optical cavity resonances. Here, we introduce an EO modulator based on piezo-strain-concentration of a photonic crystal cavity to address both trade-offs: (i) it eliminates the trade-off between d T / d V and waveguide loss—i.e., enhancement of the resonance tuning efficiency d v c / d V for the fixed EO coefficient, waveguide length, and cavity Q —and (ii) at high DC strains it exhibits a non-volatile (NV) cavity tuning Δ v c ,NV for passive memory and programming of multiple devices into resonance despite fabrication variations. The device is fabricated on a scalable silicon nitride-on-aluminum nitride platform. We measure d v c / d V =177±1MHz/V, corresponding to Δ v c =40±0.32GHz for a voltage spanning ±120V with an energy consumption of δ U /Δ v c =0.17nW/GHz. The modulation bandwidth is flat up to ω BW,3dB /2 π =3.2±0.07MHz for broadband DC-AC and 142±17MHz for resonant operation near a 2.8 GHz mechanical resonance. Optical extinction up to 25 dB is obtained via Fano-type interference. Strain-induced beam-buckling modes are programmable under a “read-write” protocol with a continuous, repeatable tuning range of 5±0.25GHz, allowing for storage and retrieval, which we quantify with mutual information of 2.4 bits and a maximum non-volatile excursion of 8 GHz. Using a full piezo-optical finite-element-model (FEM) we identify key design principles for optimizing strain-based modulators and chart a path towards achieving performance comparable to lithium niobate-based modulators and the study of high strain physics on-chip.

Wen, Y. Henry (ORCID:0009000685423628)↗
DOE OSTI2025

Exploring transport-enabled gates with integrated optical addressing to demonstrate high fidelity control of trapped ion qubits in a scalable quantum computer

In recent years, experiments involving micofabricated surface ion traps have grown in complexity, and as this complexity grows, a common design has emerged in the form of quantum charge-coupled device architecture. This architecture, already utilized on multiple systems, supports multiple zones on a device for areas such as memory or computation. The shutting process between these zones is a process often seen to be minimized. An additional component to scalable surface trapped-ion experiments includes some form of integrated photonics, as free space lasers have difficulty scaling to many ions. Here, we discuss recent results in utilizing the shuttling process with integrated photonics to perform a specific type of gate, as well as demonstrating state preparation. Furthermore, we show that these gates can be utilized as a type of optical modulator as the Doppler shift that occurs during shuttling will make the light seen by shuttled ions different than that seen by stationary ions. Furthermore, we show that the shuttling operation can be utilized as an optical modulator, where the Doppler shift changes the frequency from that of a stationary ion.

42 ENGINEERING↗
NASA NTRS1985

Advances in rechargeable lithium molybdenum disulfide batteries

The lithium molybdenum disulfide system as demonstrated in a C size cell, offers performance characteristics for applications where light weight and low volume are important. A gravimetric energy density of 90 watt hours per kilogram can be achieved in a C size cell package. The combination of charge retention capabilities, high energy density and a state of charge indicator in a rechargeable cell provides power package for a wide range of devices. The system overcomes the memory effect in Nicads where the full capacity of the battery cannot be utilized unless it was utilized on previous cycles. The development of cells with an advanced electrolyte formulation led to an improved rate capability especially at low temperatures and to a significantly improved life cycle.

Brandt, K.↗
NASA NTRS1985

Computers in Aerospace Conference, 5th, Long Beach, CA, October 21-23, 1985, Technical Papers

Among the topics discussed are: access control models for a distributed CAIS-conforming system; a knowledge-based advisory system for casualty procedures; and automated interactive simulation modeling system. Consideration is also given to: reusable software concepts and software development methodologies; the electronic device aspects of neutral network memories; an expert system for automated satellite anomaly resolution; and the use of automatic programming techniques for fault-tolerant computing systems. Among additional topics discussed are: systems approaches to software fault tolerance; a Space Shuttle navigation validation system; and a vision-based road following system for an autonomous land vehicle.

Source record↗
NASA NTRS1990

Temperature Dependence Of Single-Event Effects

Report describes experimental study of effects of temperature on vulnerability of integrated-circuit memories and other electronic logic devices to single-event effects - spurious bit flips or latch-up in logic state caused by impacts of energetic ions. Involved analysis of data on 14 different device types. In most cases examined, vulnerability to these effects increased or remain constant with temperature.

Coss, James R.↗
NASA NTRS1992

Coupling device with improved thermal interface

The primary object of the present invention is to provide a simple, reliable, and lightweight coupling that will also have an efficient thermal interface. A further object of the invention is to provide a coupling that is capable of blind mating with little or no insertion forces. Another object of the invention is to provide a coupling that acts as a thermal regulator to maintain a constant temperature on one side of the coupling. Another object of the invention is to increase the available surface area of a coupling thus providing a larger area for the conduction of heat across the thermal interface. Another object of the invention is to provide a fluidic coupling that has no fluid passing across the interface, thus reducing the likelihood of leaks and contamination. The foregoing objects are achieved by utilizing, as in the prior art, a hot area (at an elevated temperature as compared to a cold area) with a need to remove excess heat from the hot area to a cold area. In this device, the thermal interface will occur not on a planar horizontal surface, but along a non-planar vertical surface, which will reduce the reaction forces and increase the thermal conductivity of the device. One non-planar surface is a surface on a cold pin extending from the cold area and the other non-planar surface is a surface on a hot pin extending from the hot area. The cold pin is fixed and does not move while the hot pin is a flexible member and its movement towards the cold pin will bring the two non-planar surfaces together forming the thermal interface. The actuating member for the device is a shape-memory actuation wire which is attached through an aperture to the hot pin and through another aperture to an actuation wire retainer. By properly programming the actuation wire, heat from the hot area will cause the actuation wire to bend the hot wire. Heat from the hot area will cause the actuation wire to bend the hot pin towards the cold pin forming the coupling and the desired thermal interface. The shape-memory actuation wire is made of a shape-memory-effect alloy such as Nitinol.

Milam, Malcolm Bruce↗
NASA NTRS2005

Reconfigurable Processing Module

To accommodate a wide spectrum of applications and technologies, NASA s Exploration System's Missions Directorate has called for reconfigurable and modular technologies to support future missions to the moon and Mars. In response, Langley Research Center is leading a program entitled Reconfigurable Scaleable Computing (RSC) that is centered on the development of FPGA-based computing resources in a stackable form factor. This paper details the architecture and implementation of the Reconfigurable Processing Module (RPM), which is the key element of the RSC system. The RPM is an FPGA-based, space-qualified printed circuit assembly leveraging terrestrial/commercial design standards into the space applications domain. The form factor is similar to, and backwards compatible with, the PCI-104 standard utilizing only the PCI interface. The size is expanded to accommodate the required functionality while still better than 30% smaller than a 3U CompactPCI(TradeMark)card and without the overhead of the backplane. The architecture is built around two FPGA devices, one hosting PCI and memory interfaces, and another hosting mission application resources; both of which are connected with a high-speed data bus. The PCI interface FPGA provides access via the PCI bus to onboard SDRAM, flash PROM, and the application resources; both configuration management as well as runtime interaction. The reconfigurable FPGA, referred to as the Application FPGA - or simply "the application" - is a radiation-tolerant Xilinx Virtex-4 FX60 hosting custom application specific logic or soft microprocessor IP. The RPM implements various SEE mitigation techniques including TMR, EDAC, and configuration scrubbing of the reconfigurable FPGA. Prototype hardware and formal modeling techniques are used to explore the performability trade space. These models provide a novel way to calculate quality-of-service performance measures while simultaneously considering fault-related behavior due to SEE soft errors.

Somervill, Kevin↗
NASA NTRS2006

General Aviation Data Framework

The Flight Research Services Directorate at the NASA Langley Research Center (LaRC) provides development and operations services associated with three general aviation (GA) aircraft used for research experiments. The GA aircraft includes a Cessna 206X Stationair, a Lancair Colombia 300X, and a Cirrus SR22X. Since 2004, the GA Data Framework software was designed and implemented to gather data from a varying set of hardware and software sources as well as enable transfer of the data to other computers or devices. The key requirements for the GA Data Framework software include platform independence, the ability to reuse the framework for different projects without changing the framework code, graphics display capabilities, and the ability to vary the interfaces and their performance. Data received from the various devices is stored in shared memory. This paper concentrates on the object oriented software design patterns within the General Aviation Data Framework, and how they enable the construction of project specific software without changing the base classes. The issues of platform independence and multi-threading which enable interfaces to run at different frame rates are also discussed in this paper.

Blount, Elaine M.↗