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At least 523 records · Page 29

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NASA NTRS2018

Sixty Earth-Days Test of a Prototype Pt/HTCC Alumina Package in Simulated Venus Environment

This paper presents experimental results of a prototype high temperature co-fired ceramic (HTCC) package with Au/Pt metallization in a three-phase harsh environment test that culminated with 60-day demonstration in simulated Venus surface environment of 465 degrees Centigrade with corrosive atmosphere at 90 bars pressure. The prototype package is based on a previously developed and reported HTCC package successfully tested with multiple analog and digital silicon carbide (SiC) high temperatures semiconductor integrated circuits (ICs) at NASA Glenn Research Center in 500 degrees Centigrade Earth air ambient for over ten thousand hours, and short-term tested at temperatures above 800 degrees Centigrade. The three-phase harsh environment test started with 48 hours in 465 degrees Centigrade Earth air, followed by 48 hours in 465 degrees Centigrade nitrogen at 90-bar pressure and 1400 hours in simulated Venus surface environment of 465 degrees Centigrade with corrosive atmosphere at 90 bars. Initial analytical results of the package materials and surfaces after exposure to the Venus environment are discussed to assess the stability of the packaging materials in the tested environments. The test in a simulated Venus environment was implemented in the NASA Glenn Extreme Environment Rig (GEER). The results of this study suggest that an effective encapsulation of areas of surface metallization and vicinities may help to improve electrical performance of a HTCC alumina packaging system in Venus environment.

Chen, Liang-Yu↗

NASA NTRS1975

Simple photometer circuits using modular electronic components

Operational and peak holding amplifiers are discussed as useful circuits for bioluminescence assays. Circuit diagrams are provided. While analog methods can give a good integration on short time scales, digital methods were found best for long term integration in bioluminescence assays. Power supplies, a general photometer circuit with ratio capability, and variations in the basic photometer design are also considered.

Wampler, J. E.↗

NASA NTRS2001

Status of the Direct Data Distribution (D(exp 3)) Experiment

NASA Glenn Research Center's Direct Data Distribution (D3) project will demonstrate an advanced, high-performance communications system that transmits information from an advanced technology payload carried by a NASA spacecraft in low Earth orbit (LEO) to a small receiving terminal on Earth. The space-based communications package will utilize a solid-state, K-band phased-array antenna that electronically steers the radiated energy beam toward a low-cost, tracking ground terminal, thereby providing agile, vibration-free, electronic steering at reduced size and weight with increased reliability. The array-based link will also demonstrate new digital processing technology that will allow the transmission of substantially increased amounts of latency-tolerant data collected from the LEO spacecraft directly to NASA field centers, principal investigators, or into the commercial terrestrial communications network. The technologies demonstrated by D3 will facilitate NASA's transition from using Government-owned communication assets to using commercial communication services. The hardware for D3 will incorporate advanced technology components developed under the High Rate Data Delivery (HRDD) Thrust Area of NASA's Office of Aerospace Technology Space Base Program at Glenn's Communications Technology Division. The flight segment components will include the electrically steerable phased-array antenna, which is being built by the Raytheon System Corporation and utilizes monolithic microwave integrated circuit (MMIC) technology operating at 19.05 GHz; and the digital encoder/modulator chipset, which uses four-channel orthogonal frequency division multiplexing (OFDM). The encoder/modulator will use a chipset developed by SICOM, Inc., which is both bandwidth and power efficient. The ground segment components will include a low-cost, open-loop tracking ground terminal incorporating a cryoreceiver to minimize terminal size without compromising receiver capability. The project is planning to hold a critical design review in the second quarter of fiscal year 2002.

Wald, Lawrence↗

NASA NTRS1995

Formal development of a clock synchronization circuit

This talk presents the latest stage in formal development of a fault-tolerant clock synchronization circuit. The development spans from a high level specification of the required properties to a circuit realizing the core function of the system. An abstract description of an algorithm has been verified to satisfy the high-level properties using the mechanical verification system EHDM. This abstract description is recast as a behavioral specification input to the Digital Design Derivation system (DDD) developed at Indiana University. DDD provides a formal design algebra for developing correct digital hardware. Using DDD as the principle design environment, a core circuit implementing the clock synchronization algorithm was developed. The design process consisted of standard DDD transformations augmented with an ad hoc refinement justified using the Prototype Verification System (PVS) from SRI International. Subsequent to the above development, Wilfredo Torres-Pomales discovered an area-efficient realization of the same function. Establishing correctness of this optimization requires reasoning in arithmetic, so a general verification is outside the domain of both DDD transformations and model-checking techniques. DDD represents digital hardware by systems of mutually recursive stream equations. A collection of PVS theories was developed to aid in reasoning about DDD-style streams. These theories include a combinator for defining streams that satisfy stream equations, and a means for proving stream equivalence by exhibiting a stream bisimulation. DDD was used to isolate the sub-system involved in Torres-Pomales' optimization. The equivalence between the original design and the optimized verified was verified in PVS by exhibiting a suitable bisimulation. The verification depended upon type constraints on the input streams and made extensive use of the PVS type system. The dependent types in PVS provided a useful mechanism for defining an appropriate bisimulation.

Miner, Paul S.↗

NASA NTRS1983

Coding for Single-Line Transmission

Digital transmission code combines data and clock signals into single waveform. MADCODE needs four standard integrated circuits in generator and converter plus five small discrete components. MADCODE allows simple coding and decoding for transmission of digital signals over single line.

Madison, L. G.↗

NASA NTRS1993

Bridging faults in BiCMOS circuits

Combining the advantages of CMOS and bipolar, BiCMOS is emerging as a major technology for many high performance digital and mixed signal applications. Recent investigations revealed that bridging faults can be a major failure mode in IC's. Effects of bridging faults in BiCMOS circuits are presented. Bridging faults between logical units without feedback and logical units with feedback are considered. Several bridging faults can be detected by monitoring the power supply current (I(sub DDQ) monitoring). Effects of bridging faults and bridging resistance on output logic levels were examined along with their effects on noise immunity.

Menon, Sankaran M.↗

NASA NTRS1980

Improved test methods for determining lightning-induced voltages in aircraft

A lumped parameter transmission line with a surge impedance matching that of the aircraft and its return lines was evaluated as a replacement for earlier current generators. Various test circuit parameters were evaluated using a 1/10 scale relative geometric model. Induced voltage response was evaluated by taking measurements on the NASA-Dryden Digital Fly by Wire F-8 aircraft. Return conductor arrangements as well as other circuit changes were also evaluated, with all induced voltage measurements being made on the same circuit for comparison purposes. The lumped parameter transmission line generates a concave front current wave with the peak di/dt near the peak of the current wave which is more representative of lightning. However, the induced voltage measurements when scaled by appropriate scale factors (peak current or di/dt) resulting from both techniques yield comparable results.

Crouch, K. E.↗

NASA NTRS2010

Inexpensive Implementation of Many Strain Gauges

It has been proposed to develop arrays of strain gauges as arrays of ordinary metal film resistors and associated electronic readout circuitry on printed circuit boards or other suitable substrates. This proposal is a by-product of a development of instrumentation utilizing metal film resistors on printed-circuit boards to measure temperatures at multiple locations. In the course of that development, it was observed that in addition to being sensitive to temperature, the metal film resistors were also sensitive to strains in the printed-circuit boards to which they were attached. Because of the low cost of ordinary metal film resistors (typically <$0.01 apiece at 2007 prices), the proposal could enable inexpensive implementation of arrays of many (e.g., 100 or more) strain gauges, possibly concentrated in small areas. For example, such an array could be designed for use as a computer keyboard with no moving parts, as a device for sensing the shape of an object resting on a surface, or as a device for measuring strains at many points on a mirror, a fuel tank, an airplane wing, or other large object. Ordinarily, the effect of strain on resistance would be regarded as a nuisance in a temperature-measuring application, and the effect of temperature on resistance would be regarded as a nuisance in a strain-measuring application. The strain-induced changes in resistance of the metal film resistors in question are less than those of films in traditional strain gauges. The main novel aspect of present proposal lies in the use of circuitry affording sufficient sensitivity to measure strain plus means for compensating for the effect of temperature. For an array of metal film resistors used as proposed, the readout circuits would include a high-accuracy analog-to-digital converter fed by a low noise current source, amplifier chain, and an analog multiplexer chain. Corrections would be provided by use of high-accuracy calibration resistors and a temperature sensor. By use of such readout circuitry, it would be possible to read the resistances of as many as 100 fixed resistors in a time interval of 1 second at a resolution much greater than 16 bits. The readout data would be processed, along with temperature calibration data, to deduce the strain on the printed-circuit board or other substrate in the areas around the resistors. It should also be possible to also deduce the temperature from the readings.

Berkun, Andrew C.↗

NASA NTRS1975

JPL transient radiation analysis by computer program (JTRAC)

Digital computer program, JTRAC, simulates time response of electronic circuit to arbitrary forcing functions which may include electrical and/or radiation stimuli. Program is designed to solve linear and nonlinear simultaneous equations which characterize mathematical models used to predict circuit response for electrical and/or radiation input.

Weinstein, S.↗

NASA NTRS1981

Ultrastable automatic frequency control

Center frequency of wideband AFC circuit drifts only hundredths of percent per day. Since circuit responds only to slow frequency drifts and modulation signal has high-pass characteristics, AFC does not interfere with normal FM operation. Stable oscillator, reset circuit, and pulse generator constitute time-averaging discriminator; digital counter in pulse generator replaces usual monostable multivibrator.

Sabourin, D. J.↗

NASA NTRS1989

Magellan/Galileo solder joint failure analysis and recommendations

On or about November 10, 1988 an open circuit solder joint was discovered in the Magellan Radar digital unit (DFU) during integration testing at Kennedy Space Center (KSC). A detailed analysis of the cause of the failure was conducted at the Jet Propulsion Laboratory leading to the successful repair of many pieces of affected electronic hardware on both the Magellan and Galileo spacecraft. The problem was caused by the presence of high thermal coefficient of expansion heat sink and conformal coating materials located in the large (0.055 inch) gap between Dual Inline Packages (DIPS) and the printed wiring board. The details of the observed problems are described and recommendations are made for improved design and testing activities in the future.

Ross, Ronald G., Jr.↗

NASA NTRS1992

A bipolar population counter using wave pipelining to achieve 2.5 x normal clock frequency

Wave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. The throughput of a 63-b CML population counter was increased from 97 to 250 MHz using wave pipelining. The internal circuit is flowthrough combinational logic. Novel CAD methods have balanced all input-to-output paths to about the same delay. This allows multiple data waves to propagate in sequence when the circuit is clocked faster than its propagation delay.

Wong, Derek C.↗

NASA NTRS1994

Parallel digital modem using multirate digital filter banks

A new class of architectures for an all-digital modem is presented in this report. This architecture, referred to as the parallel receiver (PRX), is based on employing multirate digital filter banks (DFB's) to demodulate, track, and detect the received symbol stream. The resulting architecture is derived, and specifications are outlined for designing the DFB for the PRX. The key feature of this approach is a lower processing rate then either the Nyquist rate or the symbol rate, without any degradation in the symbol error rate. Due to the freedom in choosing the processing rate, the designer is able to arbitrarily select and use digital components, independent of the speed of the integrated circuit technology. PRX architecture is particularly suited for high data rate applications, and due to the modular structure of the parallel signal path, expansion to even higher data rates is accommodated with each. Applications of the PRX would include gigabit satellite channels, multiple spacecraft, optical links, interactive cable-TV, telemedicine, code division multiple access (CDMA) communications, and others.

Sadr, Ramin↗

NASA NTRS1995

Fault Tolerant Characteristics of Artificial Neural Network Electronic Hardware

The fault tolerant characteristics of analog-VLSI artificial neural network (with 32 neurons and 532 synapses) chips are studied by exposing them to high energy electrons, high energy protons, and gamma ionizing radiations under biased and unbiased conditions. The biased chips became nonfunctional after receiving a cumulative dose of less than 20 krads, while the unbiased chips only started to show degradation with a cumulative dose of over 100 krads. As the total radiation dose increased, all the components demonstrated graceful degradation. The analog sigmoidal function of the neuron became steeper (increase in gain), current leakage from the synapses progressively shifted the sigmoidal curve, and the digital memory of the synapses and the memory addressing circuits began to gradually fail. From these radiation experiments, we can learn how to modify certain designs of the neural network electronic hardware without using radiation-hardening techniques to increase its reliability and fault tolerance.

Artificial Neural Network↗

NASA NTRS2011

RATIR: Reionization and Transients Infra-Red Camera. A New Instrument to Identify High Red-Shift GRBs

We are currently constructing the cryogenic infrared portion of the RATIR instrument at NASA's Goddard Space Flight Center (GSFC) in collaboration with University of California, Berkeley (UCB) and The University of Mexico (UNAM). The infrared instrument will consist of two 2048x2048 Hawaii 2RG detectors, one on axis and one off axis using diachronic. The detectors will be operated using state-of-the-art Teledyne SIDECAR (System Image, Digitizing, Enhancing, Controlling, And Retrieving) ASICs (Application- Specific Integrated Circuits) similar to NIRSpec on JWST. The visible portion of the instrument is currently being developed at UCB consisting of two CCD imagining cameras. Once completed, the two sections will be integrated into the RATIR instrument. Mounted on a dedicated, fully-automated 1.5-m telescope, the instrument will provide rapid (<10 min) identification of VHR GRBs allowing high-resolution spectroscopic follow-up observations with large aperture telescopes possible. The hosting Observatorio Astronomico Nacional of the Universidad Nacional Autonoma de Mexico (UNAM), located on the Sierra de San Pedro Martir in Baja California, Mexico, provides great seeing (-1 aresec), good weather, dark skies, and significant sky coverage so that RATIR will detect a significant number of Swift afterglows. While not all GRBs will be at high red shifts, the resulting light curves, combined with X-ray/UV observations, will address several open questions, including the nature of both "dark GRBs" and the GRB emission mechanism.

Rapchun, David A.↗

NASA NTRS2003

GPS Position and Heading Circuitry for Ships

Circuit boards that contain radio-frequency (RF) and digital circuitry have been developed by NASA to satisfy a requirement of the Port of Houston Authority for relatively inexpensive Global Positioning System (GPS) receivers that indicate the azimuthal headings as well as the positions of ships. The receiver design utilizes the unique architecture of the Mitel commercial chip-set, which provides for an accurate GPS-based heading-determination device. The major components include two RF front ends (each connected to a separate antenna), a surface-acoustic-wave intermediate-frequency filter between second- and third-stage mixers, a correlator, and a reduced-instruction- set computer. One of the RF front ends operates as a master, the other as a slave. Both RF front ends share a 10-MHz sinusoidal clock oscillator, which provides for more accurate carrier phase measurements between the two antennas. The outputs of the RF front ends are subjected to conventional GPS processing. The commercial-based chip-set design approach provides an inexpensive open architecture GPS platform, which can be used in developing and implementing unique GPS-heading and attitude-determination algorithms for specific applications. The heading is estimated from the GPS position solutions of the two antennas by an algorithm developed specifically for this application. If a third (and preferably a fourth) antenna were added, it would be possible to estimate the attitude of the GPS receiver in three dimensions instead of only its heading in a horizontal plane.

Cooke, Michael P.↗

NASA NTRS2001

Low Temperature Testing of a Radiation Hardened CMOS 8-Bit Flash Analog-to-Digital (A/D) Converter

Power processing electronic systems, data acquiring probes, and signal conditioning circuits are required to operate reliably under harsh environments in many of NASA:s missions. The environment of the space mission as well as the operational requirements of some of the electronic systems, such as infrared-based satellite or telescopic observation stations where cryogenics are involved, dictate the utilization of electronics that can operate efficiently and reliably at low temperatures. In this work, radiation-hard CMOS 8-bit flash A/D converters were characterized in terms of voltage conversion and offset in the temperature range of +25 to -190 C. Static and dynamic supply currents, ladder resistance, and gain and offset errors were also obtained in the temperature range of +125 to -190 C. The effect of thermal cycling on these properties for a total of ten cycles between +80 and - 150 C was also determined. The experimental procedure along with the data obtained are reported and discussed in this paper.

Gerber, Scott S.↗

NASA NTRS1984

Optical flip-flops and sequential logic circuits using a liquid crystal light valve

This paper is concerned with the application of optics to digital computing. A Hughes liquid crystal light valve is used as an active optical element where a weak light beam can control a strong light beam with either a positive or negative gain characteristic. With this device as the central element the ability to produce bistable states from which different types of flip-flop can be implemented is demonstrated. In this paper, some general comments are first presented on digital computing as applied to optics. This is followed by a discussion of optical implementation of various types of flip-flop. These flip-flops are then used in the design of optical equivalents to a few simple sequential circuits such as shift registers and accumulators. As a typical sequential machine, a schematic layout for an optical binary temporal integrator is presented. Finally, a suggested experimental configuration for an optical master-slave flip-flop array is given.

Fatehi, M. T.↗