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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 505 records · Page 28
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

ATLAS toward the High Luminosity era: challenges on electronic systems

To maximize the physics reach, the Large Hadron Collider (LHC) plans to increase its instantaneous luminosity to $7.5×10^{34} cm^{-2} s^{-1}$ and deliver $3 - 4 ab^{-1}$ of data at a center-of-mass energy of 14 TeV. To profit from this high-luminosity LHC operation with a pile-up up to 200 inelastic collisions per bunch crossing, performance of the ATLAS detector needs to be maintained and in many systems, improved. The upgraded detector will have an unprecedented output data rate of up to 200 TB/s. Real-time processing of this large data volume in a short time period is extremely challenging. New sets of both front-end and back-end electronics are required for all sub-detectors. The large number of detector channels, huge volumes of input and output data, short time available to process and transmit data, harsh radiation environment, and the need of low power consumption all impose great challenges on the designs of electronic systems.

43 PARTICLE ACCELERATORS↗
DOE OSTI2023

Novel Cascaded Ring Oscillator Vernier based TDC Architecture with a Feedthrough Reference Oscillator

Time to digital converters (TDCs) are widely used in particle physics and medical imaging to determine the relative arrival time of photons and other particles. Vernier TDCs are one of the most attractive options due to their power consumption efficiency and their small footprint. We present our newly patented innovative architecture of cascaded-stage Vernier TDCs comprised of a feedthrough reference oscillator. This architecture lead to successive Vernier measurements that result in a lower number of cycles for the same dynamic range to resolution ratio (DRRR), leading to reduced conversion time and lower jitter. To validate this architecture, a test chip was designed in 0.18~μm TSMC technology, integrating four types of cascaded Vernier TDCs with an increasing number of stages. The performance of the chip was assessed using a modular test platform specifically designed for TDCs. For comparison purposes, all TDCs were tested with a LSB of 50~ps and a dynamic range of 20~ns. The experimental results demonstrate the highest gain in performance between 1 stage Vernier and 2 stage Vernier TDCs with the precision improved from 36~ps~rms to 21~ps~rms, the maximum number of turns from 110 to 25 counts and the dead time, from 266.4~ns to 76.5~ns, on average. Adding Vernier stages is only relevant for a higher DRRR. Therefore, the 3-stage and 4-stage Vernier TDCs also show performance gains, but improvements are limited.

Scarpellini, Robin↗
DOE OSTI2021

Using Distributed Dynamic Voltage Restorers to Improve the Frequency Stability of Low-Inertia Networked Microgrids

This paper elucidates the novel concept of using distributed dynamic voltage restorers (DVRs), which are traditionally used to compensate for voltage sags, to improve the frequency stability of low-inertia networked microgrids. During frequency transients, the distributed DVRs rapidly regulate load voltages within an acceptable range, resulting in a fast change of load power consumption and helping improve frequency stability. To enable large-scale network simulation, a phasor-based model of DVRs is developed and validated against real data from a commercially available device. Finally, simulation results of a modified IEEE 123-node test feeder that comprises three microgrids and six DVRs verify the effectiveness of the proposed method.

Du, Wei↗
DOE OSTI2022

FALCON readout channel for X-ray ptychography applications

This work reports the current state of the development of a pixelated readout for nanometer resolution X-ray ptychography applications. A very dense, low-noise and low-power pixel developed in a commercial 65nm CMOS technology is envisioned for such applications, targeting a pixel area of 150 μm × 150 μm, an overall noise of 200e- rms and a power consumption of 150μW per pixel. In the paper, an introduction to the application and an overview of the experimental setup are given, the designed frontend channel is reported and revised in its components and simulation results of the schematic-level design are shown and discussed.

Lazzaroni, Paolo↗
DOE OSTI2021

Practical implications of SFQ-based two-qubit gates

Scalability of today’s superconducting quantum computers is limited due to the huge costs of generating/routing microwave control pulses per qubit from room temperature. One active research area in both industry and academia is to push the classical controllers to the dilution refrigerator in order to increase the scalability of quantum computers. Superconducting Single Flux Quantum (SFQ) is a classical logic technology with low power consumption and ultra-high speed, and thus is a promising candidate for in-fridge classical controllers with maximized scalability. Prior work has demonstrated high-fidelity SFQ-based single-qubit gates. However, little research has been done on SFQ-based multi-qubit gates, which are necessary to realize SFQ-based universal quantum computing.In this paper, we present the first thorough analysis of SFQ-based two-qubit gates. Our observations show that SFQ-based two-qubit gates tend to have high leakage to qubit non-computational subspace, which presents severe design challenges. We show that despite these challenges, we can realize gates with high fidelity by carefully designing optimal control methods and qubit architectures. We develop optimal control methods that suppress leakage, and also investigate various qubit architectures that reduce the leakage. After carefully engineering our SFQ-friendly quantum system, we show that it can achieve similar gate fidelity and gate time to microwave-based quantum systems. Furthermore, the promising results of this paper show that (1) SFQ-based universal quantum computation is both feasible and effective; and (2) SFQ is a promising approach in designing classical controller for quantum machines because it can increase the scalability while preserving gate fidelity and performance.

42 ENGINEERING↗
DOE OSTI2024

A Performance and Energy Study of GPU-Resident Preconditioners for Conjugate Gradient Solvers: In the Context of Existing and Novel Approaches

Optimizing a particular subprogram out of the set of Basic (sparse) Linear Algebra Subprograms (BLAS) for a given architecture is a common topic of research. In applications, however, these BLAS functions rarely appear in isolation; usually, many of them are used together, in various combinations and with varying inputs. As the need to solve a large, sparse linear system is ubiquitous throughout HPC applications, linear solvers constitute a realistic, sufficiently complex and well-defined representative use case for composite BLAS routines. To this end, based on a representative set of matrices drawn from a diverse set of fields, we present a framework to study, from the performance and energy perspective, the efficacy of GPU- resident parallel Conjugate Gradient (CG) linear solver with different preconditioner options, including Gauss-Seidel, Jacobi, and incomplete Cholesky. We also propose a novel GPU-based preconditioner, in which the triangular solves are approximated by an iterative process. The development of this preconditioner was motivated by solving large graph Laplacian linear systems, for which the existing preconditioners either perform slow on GPU-based platforms or are not applicable. We compare the performance of these preconditioners on different hardware accelerator architectures, i.e., AMD MI250X, MI100, Nvidia A100, V100, and Jetson. Our experiments reveal performance trade-offs and provide information on how to select the best strategy for the given linear system, dictated by its properties, and the platform of interest. We demonstrate the application of our novel preconditioner for solving CG and graph Laplacian systems. Overall, the framework can be utilized as a benchmark to guide informed decisions in choosing a specific preconditioner, i.e., whether it is better to rely on the performance of a triangular solver or on the performance of sparse matrix-vector product. Finally, by considering power consumption to solve the linear systems, we report the energy footprint for the solvers.

Preconditioned Conjugate Gradient, GPUs, iterative↗
DOE OSTI2022

Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications

Here this paper presents a superconducting, magnetically-coupled, shuttle-flux shift register (SF-SR) that stores single flux quantum (SFQ) pulses. This shift register has a DC bias operating margin of ±34% at 10 GHz, with a power dissipation of 3.6 μW and 38% fewer Josephson junctions (JJs) when scaled up to multiple stages compared to a data flip-flop (DFF) based shift register. The clock input is inductively coupled and is independent from the data input. We then present three applications for our SF-SR. In the first application, we add two non-destructive readout (NDRO) cells to construct a buffer that temporarily stores the temporal information of a series of race logic (RL) pulses. The second application is a pseudo-random number generator based on a linear function shift register (LFSR). The third application is N parallel SF-SRs that can act similar to a deserializer or instead can emulate a single SF-SR of N times higher clock frequency. These three applications motivate deep shift registers with many shifting intervals, which our SF-SR can implement with fewer JJs and lower power consumption compared to DFF-based shift registers.

42 ENGINEERING↗
DOE OSTI2023

Prototype Design of Global Common Module for ATLAS Experiment’s Phase-II Upgrade

A new Global Trigger subsystem will be installed in the Level-0 Trigger as part of HL-LHC Upgrade of ATLAS during the upcoming Long-Shutdown 3. It will feature new and improved trigger hardware and algorithms, and an increased maximum output rate of 1 MHz. The Global Trigger will run offline-like trigger algorithms on full-granularity data, gathered from several sub-detectors and trigger-processing subsystems. A single Global Common Module (GCM) hardware is implemented across the Global Trigger system to be used as Multiplexer Processor, Global Event Processor and CTP Interface (gCTPi). This common hardware platform method will minimize the complexity of the firmware and simplify the system design and long-term maintenance. The GCM prototype is an ATCA front form factor board with two Xilinx Virtex UltraScale+ FPGA VU13P and one ZYNQ UltraScale+ FPGA ZU19EG and seventeen 25.78125 Gb/s FireFly duplex optical modules on it. The total power consumption of this board must be less than 350 W, and the temperature of the optical modules should be less than 70 °C in the worst case. The VU13Ps serve as algorithms processor nodes such as MUX, GEP and gCTPi, and the ZU19EG with Peta Linux OS running on it, is used as Command/Control/Readout Unit to configure and monitor the board and communicate with the ATLAS Detector Control System (DCS). The development of an ATCA blade with three large FPGAs and about 200 optical links running at 25Gb/s is a very challenging task, and the successful test results have demonstrated this GCM prototype as an advancement of state-of-the-art electronics module design in HEP experiments. This paper presents the hardware design considerations, functionalities, and performance test results of this GCM prototype.

47 OTHER INSTRUMENTATION↗
DOE OSTI2021

ARENA: Asynchronous Reconfigurable Accelerator Ring to Enable Data-Centric Parallel Computing

The next generation HPC and data centers are likely to be reconfigurable and data-centric due to the trend of hardware specialization and the emergence of data-driven applications. In this work, we propose ARENA – an asynchronous reconfigurable accelerator ring architecture as a potential scenario on how the future HPC and data centers will be like. Despite using the coarse-grained reconfigurable arrays (CGRAs) as the substrate platform, our key contribution is not only the CGRA-cluster design itself, but also the ensemble of a new architecture and programming model that enables asynchronous tasking across a cluster of reconfigurable nodes, so as to bring specialized computation to the data rather than the reverse. We presume distributed data storage without asserting any prior knowledge on the data distribution. Hardware specialization occurs at runtime when a task finds the majority of data it requires are available at the present node. In other words, we dynamically generate specialized CGRA accelerators where the data reside. The asynchronous tasking for bringing computation to data is achieved by circulating the task token, which describes the dataflow graphs to be executed for a task, among the CGRA cluster connected by a fast ring network. Evaluations on a set of HPC and data-driven applications across different domains show that ARENA can provide better parallel scalability with reduced data movement (53.9 percent). Compared with contemporary compute-centric parallel models, ARENA can bring on average 4.37× speedup. The synthesized CGRAs and their task-dispatchers only occupy 2.93mm 2 chip area under 45nm process technology and can run at 800MHz with on average 759.8mW power consumption. ARENA also supports the concurrent execution of multi-applications, offering ideal architectural support for future high-performance parallel computing and data analytics systems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

A new open‐path eddy covariance method for nitrous oxide and other trace gases that minimizes temperature corrections

Abstract Low‐power, open‐path gas sensors enable eddy covariance (EC) flux measurements in remote areas without line power. However, open‐path flux measurements are sensitive to fluctuations in air temperature, pressure, and humidity. Laser‐based, open‐path sensors with the needed sensitivity for trace gases like methane (CH 4 ) and nitrous oxide (N 2 O) are impacted by additional spectroscopic effects. Corrections for these effects, especially those related to temperature fluctuations, often exceed the flux of gases, leading to large uncertainties in the associated fluxes. For example, the density and spectroscopic corrections arising from temperature fluctuations can be one or two orders of magnitude greater than background N 2 O fluxes. Consequently, measuring background fluxes with laser‐based, open‐path sensors is extremely challenging, particularly for N 2 O and gases with similar high‐precision requirements. We demonstrate a new laser‐based, open‐path N 2 O sensor and a general approach applicable to other gases that minimizes temperature‐related corrections for EC flux measurements. The method identifies absorption lines with spectroscopic effects in the opposite direction of density effects from temperature and, thus, density and spectroscopic effects nearly cancel one another. The new open‐path N 2 O sensor was tested at a corn ( Zea mays L.) field in Southwestern Michigan, United States. The sensor had an optimal precision of 0.1 ppbv at 10 Hz and power consumption of 50 W. Field trials showed that temperature‐related corrections were 6% of density corrections, reducing EC random errors by 20‐fold compared to previously examined lines. Measured open‐path N 2 O EC fluxes showed excellent agreement with those made with static chambers ( m = 1.0 ± 0.3; r 2 = .96). More generally, we identified absorption lines for CO 2 and CH 4 flux measurements that can reduce the temperature‐related corrections by 10–100 times compared to existing open‐path sensors. The proposed method provides a new direction for future open‐path sensors, facilitating the expansion of accurate EC flux measurements.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Conversion degree and heat transfer in the cold cap and their effect on glass production rate in an electric melter

A predictive model of melt rate in waste glass vitrification operations is needed to inform melter operations during normal and off-normal operations. This paper describes the development of a model of the cold cap (the reacting melter feed floating on molten glass in a glass melter) that couples heat transfer with the feed-to-glass conversion kinetics. The model was applied to four melter feeds designed for high-level and low-activity nuclear waste feeds using the material properties, either measured or estimated, to obtain temperature and conversion distribution within the cold cap. The cold cap model, when coupled with a computational fluid dynamics model of a Joule-heated glass melter, allows the prediction of the glass production rate and power consumption. The results show reasonable agreement with the melting rates measured during pilot-scale melter tests.

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗
DOE OSTI2020

Magnetizing lead-free halide double perovskites

Spintronics holds great potential for next-generation high-speed and low–power consumption information technology. Recently, lead halide perovskites (LHPs), which have gained great success in optoelectronics, also show interesting magnetic properties. However, the spin-related properties in LHPs originate from the spin-orbit coupling of Pb, limiting further development of these materials in spintronics. Here, we demonstrate a new generation of halide perovskites, by alloying magnetic elements into optoelectronic double perovskites, which provide rich chemical and structural diversities to host different magnetic elements. In our iron-alloyed double perovskite, Cs 2 Ag(Bi:Fe)Br 6 , Fe 3+ replaces Bi 3+ and forms FeBr 6 clusters that homogenously distribute throughout the double perovskite crystals. Furthermore, we observe a strong temperature-dependent magnetic response at temperatures below 30 K, which is tentatively attributed to a weak ferromagnetic or antiferromagnetic response from localized regions. We anticipate that this work will stimulate future efforts in exploring this simple yet efficient approach to develop new spintronic materials based on lead-free double perovskites.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Aligned 2D carbon nanotube liquid crystals for wafer-scale electronics

Semiconducting carbon nanotubes promise faster performance and lower power consumption than Si in field-effect transistors (FETs) if they can be aligned in dense arrays. Here, we demonstrate that nanotubes collected at a liquid/liquid interface self-organize to form two-dimensional (2D) nematic liquid crystals that globally align with flow. The 2D liquid crystals are transferred onto substrates in a continuous process generating dense arrays of nanotubes aligned within ±6°, ideal for electronics. Nanotube ordering improves with increasing concentration and decreasing temperature due to the underlying liquid crystal phenomena. The excellent alignment and uniformity of the transferred assemblies enable FETs with exceptional on-state current density averaging 520 μA μm -1 at only -0.6 V, and variation of only 19%. FETs with ion gel top gates demonstrate subthreshold swing as low as 60 mV decade -1 . Deposition across a 10-cm substrate is achieved, evidencing the promise of 2D nanotube liquid crystals for commercial semiconductor electronics.

42 ENGINEERING↗
DOE OSTI2024

Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines

Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)–based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Neuromorphic Graph Algorithms: Cycle Detection, Odd Cycle Detection, and Max Flow

Neuromorphic computing is poised to become a promising computing paradigm in the post Moore’s law era due to its extremely low power usage and inherent parallelism. Spiking neural networks are the traditional use case for neuromorphic systems, and have proven to be highly effective at machine learning tasks such as control problems. More recently, neuromorphic systems have been applied outside of the arena of machine learning, primarily in the field of graph algorithms. Neuromorphic systems have been shown to perform graph algorithms faster and with lower power consumption than their traditional (GPU/CPU) counterparts, and are hence an attractive option for a co-processing unit in future high performance computing systems, where graph algorithms play a critical role. In this paper, we present a neuromorphic implementation of cycle detection, odd cycle detection, and the Ford-Fulkerson max-flow algorithm. We further evaluate the performance of these implementations using the NEST neuromorphic simulator by using spike counts and simulation time as proxies for energy consumption and run time. In addition to gains inherent in neuromorphic systems, we show that within the neuromorphic implementations early stopping criteria can be implemented to further improve performance.

Kay, Bill↗
DOE OSTI2023

SwitchX : Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars

Memristive crossbars can efficiently implement Binarized Neural Networks (BNNs) wherein the weights are stored in high-resistance states (HRS) and low-resistance states (LRS) of the synapses. We propose SwitchX mapping of BNN weights onto ReRAM crossbars such that the impact of crossbar non-idealities, that lead to degradation in computational accuracy, are minimized. Essentially, SwitchX maps the binary weights in such a manner that a crossbar instance comprises of more HRS than LRS synapses. We find BNNs mapped onto crossbars with SwitchX to exhibit better robustness against adversarial attacks than the standard crossbar mapped BNNs, the baseline. Finally, we combine SwitchX with state-aware training (that further increases the feasibility of HRS states during weight mapping) to boost the robustness of a BNN on hardware. We find that this approach yields stronger defense against adversarial attacks than adversarial training, a state-of the-art software defense. We perform experiments on a VGG16 BNN with benchmark datasets (CIFAR-10, CIFAR-100 and TinyImagenet) and use Fast Gradient Sign Method (ϵ = 0.05 to 0.3) and Projected Gradient Descent (ϵ = $\frac{2}{255}$ to $\frac{32}{255}$, α = $\frac{2}{255}$) adversarial attacks. We show that SwitchX combined with state-aware training can yield upto ~35% improvements in clean accuracy and ~6–16% in adversarial accuracies against conventional BNNs. Furthermore, an important by-product of SwitchX mapping is increased crossbar power savings, owing to an increased proportion of HRS synapses, which is furthered with state-aware training. We obtain upto ~21–22% savings in crossbar power consumption for state-aware trained BNN mapped via SwitchX on 16 × 16 and 32 × 32 crossbars using the CIFAR-10 and CIFAR-100 datasets.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Understanding GPU Memory Corruption at Extreme Scale: The Summit Case Study

GPU memory corruption and in particular double-bit errors (DBEs) remain one of the least understood aspects of HPC system reliability. Albeit rare, their occurrences always lead to job termination and can potentially cost thousands of node-hours, either from wasted computations or as the overhead from regular checkpointing needed to minimize the losses. As supercomputers and their components simultaneously grow in scale, density, failure rates, and environmental footprint, the efficiency of HPC operations becomes both an imperative and a challenge. We examine DBEs using system telemetry data and logs collected from the Summit supercomputer, equipped with 27,648 Tesla V100 GPUs with 2nd-generation high-bandwidth memory (HBM2). Using exploratory data analysis and statistical learning, we extract several insights about memory reliability in such GPUs. We find that GPUs with prior DBE occurrences are prone to experience them again due to otherwise harmless factors, correlate this phenomenon with GPU placement, and suggest manufacturing variability as a factor. On the general population of GPUs, we link DBEs to short- and long-term high power consumption modes while finding no significant correlation with higher temperatures. We also show that the workload type can be a factor in memory’s propensity to corruption.

Oles, Vlad↗
DOE OSTI2025

ChemComp: A Compilation Framework for Computing with Chemical Reaction Networks

The acceleration of scientific computation, data analytics, and artificial intelligence is driving a surge in computational requirements. Yet, state-of-the-art high-performance computing systems are approaching physical limitations that impede further significant improvements in energy efficiency. As we move towards post-exascale computing systems, innovative approaches are necessary to overcome this barrier in power consumption. Novel analog and hybrid digital-analog architectures hold promise for enhancing energy efficiency by several orders of magnitude. Biochemical computation stands out among the various solutions being explored due to its potential to enable new classes of devices with immense computational capabilities. These devices can capitalize on the inherent efficacy of biological cells in solving optimization problems and are scalable through increasing reaction system size or vessel capacity, potentially satisfying scientific computing's high-performance requirements. Nonetheless, several theoretical and practical limitations persist, including problem formulation and mapping to chemical reaction networks (CRNs) and implementation of actual CRN devices. In this paper, we propose a framework for biochemical computation using systems chemistry. We present the initial components of our approach: an abstract chemical reaction dialect implemented as a multi-level intermediate representation (MLIR) compiler extension and a pathway to represent mathematical problems with CRNs. To showcase the potential of this approach, we emulate a simplified chemical reservoir device. This work lays the groundwork for leveraging chemistry's computing potential in creating energy-efficient, high-performance computing systems tailored to contemporary computational needs.

artificial intelligence↗