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At least 505 records · Page 28

The MSFC complementary metal oxide semiconductor (including multilevel interconnect metallization) process handbook

The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included.

Bouldin, D. L.↗

PC based graphic display real-time particle beam uniformity

A technique has been developed to support the study of the effects of cosmic rays on integrated circuits. The system is designed to determine the particle distribution across the surface of an integrated circuit accurately while the circuit is bombarded by a particle beam. The system uses photomultiplier tubes, an octal discriminator, a computer-controlled NIM quad counter, and an IBM PC. It provides real-time operator feedback for fast beam tuning and monitors momentary fluctuations in the particle beam. The hardware, software, and system performance are described.

Huebner, M. A.↗

Oblique Eccentric Gaze Holding Evokes Larger Horizontal than Vertical Rebound Nystagmus

Rebound nystagmus (RN) has been used to probe the adaptation mechanisms of the gaze holding system. This type of nystagmus is invoked upon returning to central gaze after prolonged fixation at an eccentric point and it is thought to reflect a set-point adaptation of the neural integrator circuit. Previous studies have only observed horizontal RN after horizontal eccentric gaze holding, reflecting adaptation of the horizontal neural integrator. The current study seeks to elucidate how eccentric gaze at oblique target locations, where there are equal horizontal and vertical components, affects the characteristics of the resulting RN. For a given trial, subjects were instructed to fixate a central flashing target for 5 seconds, then fixate an eccentric continuous target for 30 seconds at one of six possible locations (4 oblique and 2 horizontal targets), and finally fixate centrally at a flashing target for 15 seconds where RN is assessed. Binocular eye-tracking data were collected at 250 Hz. Slow-phase velocity (SPV) or the slow drift part of the nystagmus was used to quantify the magnitude of RN. Subjects showed elevated SPV in the horizontal component (2.3 deg/s), but less in the vertical component (1.4 deg/s) after oblique eccentric gaze holding, reflecting an oblique RN. The smaller vertical RN may reflect a different behavior of the horizontal and vertical neural integrators which are anatomically separated. Under the current paradigm, oblique gaze holding would appear to have a smaller effect on adaptation of the vertical integrator than in the horizontal integrator. Further investigation is needed to establish the reference frame of this distinction between the horizontal and vertical integrator circuits.

gaze holding↗

Optoelectronic Infrastructure for Radio Frequency and Optical Phased Arrays

Optoelectronic integrated circuits offer radiation-hardened solutions for satellite systems in addition to improved size, weight, power, and bandwidth characteristics. ODIS, Inc., has developed optoelectronic integrated circuit technology for sensing and data transfer in phased arrays. The technology applies integrated components (lasers, amplifiers, modulators, detectors, and optical waveguide switches) to a radio frequency (RF) array with true time delay for beamsteering. Optical beamsteering is achieved by controlling the current in a two-dimensional (2D) array. In this project, ODIS integrated key components to produce common RF-optical aperture operation.

Cai, Jianhong↗

A complementary MOS process

The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated circuits is described. The fixed-gate array concept is presented as a means of obtaining CMOS integrated circuits in a fast and reliable fashion. Examples of CMOS circuits fabricated by both the conventional method and the fixed-gate array method are included. The electrical parameter specifications and characteristics are given along with typical values used to produce CMOS circuits. Temperature-bias stressing data illustrating the thermal stability of devices manufactured by this process are presented. Results of a preliminary study on the radiation sensitivity of circuits manufactured by this process are discussed. Some process modifications are given which have improved the radiation hardness of our CMOS devices. A formula description of the chemicals and gases along with the gas flow rates is also included.

Jhabvala, M. D.↗

Total-dose radiation effects data for semiconductor devices. 1985 supplement. Volume 2, part A

Steady-state, total-dose radiation test data, are provided in graphic format for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. This volume provides data on integrated circuits. The data are presented in graphic, tabular, and/or narrative format, depending on the complexity of the integrated circuit. Most tests were done using the JPL or Boeing electron accelerator (Dynamitron) which provides a steady-state 2.5 MeV electron beam. However, some radiation exposures were made with a Cobalt-60 gamma ray source, the results of which should be regarded as only an approximate measure of the radiation damage that would be incurred by an equivalent electron dose.

Martin, K. E.↗

Total-dose radiation effects data for semiconductor devices. 1985 Supplement. Volume 2, part B

Steady-state, total-dose radiation test data are provided in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. The document is in two volumes: Volume 1 provides data on diodes, bipolar transistors, field effect transistors, and miscellaneous semiconductor types, and Volume 2 (Parts A and B) provides data on integrated circuits. The data are presented in graphic, tabular, and/or narrative format, depending on the complexity of the integrated circuit. Most tests were done steady-state 2.5-MeV electron beam. However, some radiation exposures were made with a Cobalt-60 gamma ray source, the results of which should be regarded as only an approximate measure of the radiation damage that would be incurred by an equivalent electron dose. All data were generated in support of NASA space programs by the JPL Radiation Effects and Testing Group (514).

Martin, K. E.↗

Rotary blood pump

A rotary blood pump is presented. The pump includes a pump housing for receiving a flow straightener, a rotor mounted on rotor bearings and having an inducer portion and an impeller portion, and a diffuser. The entrance angle, outlet angle, axial, and radial clearances of the blades associated with the flow straightener, inducer portion, impeller portion, and diffuser are optimized to minimize hemolysis while maintaining pump efficiency. The rotor bearing includes a bearing chamber that is filled with crosslinked blood or other bio-compatible material. A back emf integrated circuit regulates rotor operation and a microcomputer may be used to control one or more back emf integrated circuits. A plurality of magnets are disposed in each of a plurality of impeller blades with a small air gap. A stator may be axially adjusted on the pump housing to absorb bearing load and maximize pump efficiency.

Bozeman, Richard J.↗

Rotary Blood Pump

A rotary blood pump includes a pump housing for receiving a flow straightener, a rotor mounted on rotor bearings and having an inducer portion and an impeller portion, and a diffuser. The entrance angle, outlet angle, axial and radial clearances of blades associated with the flow straightener, inducer portion, impeller portion and diffuser are optimized to minimize hemolysis while maintaining pump efficiency. The rotor bearing includes a bearing chamber that is filled with cross-linked blood or other bio-compatible material. A back emf integrated circuit regulates rotor operation and a microcomputer may be used to control one or more back emf integrated circuits. A plurality of magnets are disposed in each of a plurality of impeller blades with a small air gap. A stator may be axially adjusted on the pump housing to absorb bearing load and maximize pump efficiency.

Bozeman, Richard J., Jr.↗

Axial Pump

A rotary blood pump includes a pump housing for receiving a flow straightener, a rotor mounted on rotor bearings and having an inducer portion and an impeller portion, and a diffuser. The entrance angle, outlet angle, axial and radial clearances of blades associated with the flow straightener, inducer portion, impeller portion and diffuser are optimized to minimize hemolysis while maintaining pump efficiency. The rotor bearing includes a bearing chamber that is filled with cross-linked blood or other bio-compatible material. A back emf integrated circuit regulates rotor operation and a microcomputer may be used to control one or more back emf integrated circuits. A plurality of magnets are disposed in each of a plurality of impeller blades with a small air gap. A stator may be axially adjusted on the pump housing to absorb bearing load and maximize pump efficiency.

Bozeman, Richard J., Jr.↗

A miniaturized neuroprosthesis suitable for implantation into the brain

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 x 400-microm pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1 degree C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

Action Potentials/physiology↗

Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Patterson, Richard↗

Multiple-Bit Errors Caused By Single Ions

Report describes experimental and computer-simulation study of multiple-bit errors caused by impingement of single energetic ions on 256-Kb dynamic random-access memory (DRAM) integrated circuit. Studies illustrate effects of different mechanisms for transport of charge from ion tracks to various elements of integrated circuits. Shows multiple-bit errors occur in two different types of clusters about ion tracks causing them.

Zoutendyk, John A.↗

Feed Structure For Antennas

A novel feed structure, for an antenna having a resonant electric field structure, comprising a patch element, an integrated circuit attached to the patch element, at least one inner conductor electrically connected to and terminating at the integrated circuit on a first end of the at least one inner conductor, wherein the at least one inner conductor extends through and is not electrically connected to the patch element, and wherein the at least one inner conductor is available for electrical connectivity on a second end of the at least one inner conductor, and an outer conductor electrically connected to and terminating at the patch element on a first end of the outer conductor, wherein the outer conductor is available for electrical connectivity on a second end of the outer conductor, and wherein the outer conductor concentrically surrounds the at least one inner conductor from the second end of the at least one inner conductor available for electrical connectivity to the first end of the outer conductor terminating at the patch element.

Patrick W Fink↗

Innovative, Inexpensive Etching Technique Developed for Polymer Electro- Optical Structures

Electro-optic, polymer-based integrated optic devices for high-speed communication and computing applications offer potentially significant advantages over conventional inorganic electro-optic crystals. One key area of integrated optical technology--primary processing and fabrication--may particularly benefit from the use of polymer materials. However, as efforts concentrate on the miniaturization of electro-integrated circuit pattern geometries, the ability to etch fine features and smoothly sloped sidewalls is essential to make polymers useful for electro-integrated circuit applications. There are many existing processes available to etch polymer materials, but they all yield nearly vertical sidewalls. Vertical sidewalls are too difficult to reliably cover with a metal layer, and incomplete metalization degrades microwave performance, particularly at high frequency. However, obtaining a very sloped sidewall greatly improves the deposition of metal on the sidewall, leading to low-loss characteristics, which are essential to integrating these devices in highspeed electro-optic modulators. The NASA Lewis Research Center has developed in-house an inexpensive etching technique that uses a photolithography method followed by a simple, wet chemical etching process to etch through polymer layers. In addition to being simpler and inexpensive, this process can be used to fabricate smoothly sloped sidewalls by using a commercial none rodible mask: Spin-On-Glass. A commercial transparent material, Spin-On-Glass, uses processes and equipment similar to that for photoresist techniques.

Nguyen, Hung D.↗

System Measures Logic-Gate Delays

Many gates on chip tested automatically. Automatic testing system measures signal-propagation delays of experimental integrated-circuit array of logic gates. Includes controlling computer, counter/time, and feedback-controlled timing-waveform generator. Multiplexer included on integrated-circuit chip with logic-gate array to be tested. Delays measured by system serve as valuable data for design of fast logic and memory chips.

Blaes, Brent R.↗

Assessment of SOI Devices and Circuits at Extreme Temperatures

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

Elbuluk, Malik↗