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All sources NASA NTRS DOE OSTI

DOE OSTI2025

Graph decomposition techniques for solving combinatorial optimization problems with variational quantum algorithms

The quantum approximate optimization algorithm (QAOA) has the potential to approximately solve complex combinatorial optimization problems in polynomial time. However, current noisy quantum devices cannot solve large problems due to hardware constraints. In this work, we develop an algorithm that decomposes the QAOA input problem graph into a smaller problem and solves MaxCut using QAOA on the reduced graph. The algorithm requires a subroutine that can be classical or quantum—in this work, we implement the algorithm twice on each graph. One implementation uses the classical solver Gurobi in the subroutine and the other uses QAOA. We solve these reduced problems with QAOA. On average, the reduced problems require only approximately 1/10 of the number of vertices than the original MaxCut instances. Furthermore, the average approximation ratio of the original MaxCut problems is 0.75, while the approximation ratios of the decomposed graphs are on average of 0.96 for both Gurobi and QAOA. With this decomposition, we are able to measure optimal solutions for ten 100-vertex graphs by running single-layer QAOA circuits on the Quantinuum trapped-ion quantum computer H1-1, sampling each circuit only 500 times. This approach is best suited for sparse, particularly k-regular graphs, as k-regular graphs on n vertices can be decomposed into a graph with at most $\frac{nk}{k+1}$ vertices in polynomial time. Further reductions can be obtained with a potential trade-off in computational time. In conclusion, while this paper applies the decomposition method to the MaxCut problem, it can be applied to more general classes of combinatorial optimization problems.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1985

Solution of partial differential equations on vector and parallel computers

The present status of numerical methods for partial differential equations on vector and parallel computers was reviewed. The relevant aspects of these computers are discussed and a brief review of their development is included, with particular attention paid to those characteristics that influence algorithm selection. Both direct and iterative methods are given for elliptic equations as well as explicit and implicit methods for initial boundary value problems. The intent is to point out attractive methods as well as areas where this class of computer architecture cannot be fully utilized because of either hardware restrictions or the lack of adequate algorithms. Application areas utilizing these computers are briefly discussed.

Ortega, J. M.↗

NASA NTRS1985

Solution of partial differential equations on vector and parallel computers

Ortega, J. M.↗

DOE OSTI2024

Noise-induced transition in optimal solutions of variational quantum algorithms

Variational quantum algorithms are promising candidates for delivering practical quantum advantage on noisy intermediate-scale quantum (NISQ) hardware. However, optimizing the noisy cost functions associated with these algorithms is challenging for system sizes relevant to quantum advantage. In this work, we investigate the effect of noise on optimization by studying a variational quantum eigensolver (VQE) algorithm calculating the ground state of a spin chain model, and we observe an abrupt transition induced by noise to the optimal solutions. We will present numerical simulations, a demonstration using an IBM quantum processor unit (QPU), and a theoretical analysis indicating the origin of this transition. Our findings suggest that careful analysis is crucial to avoid misinterpreting the noise-induced features as genuine algorithm results.

Li, Andy C.Y.↗

NASA NTRS1974

MIDAS, prototype Multivariate Interactive Digital Analysis System, Phase 1. Volume 2: Diagnostic system

The MIDAS System is a third-generation, fast, multispectral recognition system able to keep pace with the large quantity and high rates of data acquisition from present and projected sensors. A principal objective of the MIDAS Program is to provide a system well interfaced with the human operator and thus to obtain large overall reductions in turn-around time and significant gains in throughout. The hardware and software generated in Phase I of the over-all program are described. The system contains a mini-computer to control the various high-speed processing elements in the data path and a classifier which implements an all-digital prototype multivariate-Gaussian maximum likelihood decision algorithm operating 2 x 105 pixels/sec. Sufficient hardware was developed to perform signature extraction from computer-compatible tapes, compute classifier coefficients, control the classifier operation, and diagnose operation. Diagnostic programs used to test MIDAS' operations are presented.

Kriegler, F. J.↗

NASA NTRS2012

Simulation and Flight Test Capability for Testing Prototype Sense and Avoid System Elements

NASA Langley Research Center (LaRC) and The MITRE Corporation (MITRE) have developed, and successfully demonstrated, an integrated simulation-to-flight capability for evaluating sense and avoid (SAA) system elements. This integrated capability consists of a MITRE developed fast-time computer simulation for evaluating SAA algorithms, and a NASA LaRC surrogate unmanned aircraft system (UAS) equipped to support hardware and software in-the-loop evaluation of SAA system elements (e.g., algorithms, sensors, architecture, communications, autonomous systems), concepts, and procedures. The fast-time computer simulation subjects algorithms to simulated flight encounters/ conditions and generates a fitness report that records strengths, weaknesses, and overall performance. Reviewed algorithms (and their fitness report) are then transferred to NASA LaRC where additional (joint) airworthiness evaluations are performed on the candidate SAA system-element configurations, concepts, and/or procedures of interest; software and hardware components are integrated into the Surrogate UAS research systems; and flight safety and mission planning activities are completed. Onboard the Surrogate UAS, candidate SAA system element configurations, concepts, and/or procedures are subjected to flight evaluations and in-flight performance is monitored. The Surrogate UAS, which can be controlled remotely via generic Ground Station uplink or automatically via onboard systems, operates with a NASA Safety Pilot/Pilot in Command onboard to permit safe operations in mixed airspace with manned aircraft. An end-to-end demonstration of a typical application of the capability was performed in non-exclusionary airspace in October 2011; additional research, development, flight testing, and evaluation efforts using this integrated capability are planned throughout fiscal year 2012 and 2013.

Howell, Charles T.↗

DOE OSTI2021

A Software Framework for Comparing Training Approaches for Spiking Neuromorphic Systems

There are a wide variety of training approaches for spiking neural networks for neuromorphic deployment. However, it is often not clear how these training algorithms perform or compare when applied across multiple neuromorphic hardware platforms and multiple datasets. In this work, we present a software framework for comparing performance across four neuromorphic training algorithms across three neuromorphic simulators and four simple classification tasks. We introduce an approach for training a spiking neural network using a decision tree, and we compare this approach to training algorithms based on evolutionary algorithms, back-propagation, and reservoir computing. We present a hyperparameter optimization approach to tune the hyperparameters of the algorithm, and show that these optimized hyperparameters depend on the processor, algorithm, and classification task. Finally, we compare the performance of the optimized algorithms across multiple metrics, including accuracy, training time, and resulting network size, and we show that there is not one best training algorithm across all datasets and performance metrics.

Schuman, Catherine↗

DOE OSTI2025

Stochastic noise can be helpful for variational quantum algorithms

Saddle points constitute a crucial challenge for first-order gradient descent algorithms. In notions of classical machine learning, they are avoided, for example, by means of stochastic gradient descent methods. In this work, we provide evidence that the saddle-points problem can be naturally avoided in variational quantum algorithms by exploiting the presence of stochasticity. We prove convergence guarantees and present practical examples in numerical simulations and on quantum hardware. We argue that the natural stochasticity of variational algorithms can be beneficial for avoiding strict saddle points, i.e., those saddle points with at least one negative Hessian eigenvalue. This insight that some levels of shot noise could help is expected to add a new perspective to notions of near-term variational quantum algorithms. Published by the American Physical Society 2025

Liu, Junyu↗

NASA NTRS1990

The environmental control and life support system advanced automation project. Phase 1: Application evaluation

The Environmental Control and Life Support System (ECLSS) is a Freedom Station distributed system with inherent applicability to advanced automation primarily due to the comparatively large reaction times of its subsystem processes. This allows longer contemplation times in which to form a more intelligent control strategy and to detect or prevent faults. The objective of the ECLSS Advanced Automation Project is to reduce the flight and ground manpower needed to support the initial and evolutionary ECLS system. The approach is to search out and make apparent those processes in the baseline system which are in need of more automatic control and fault detection strategies, to influence the ECLSS design by suggesting software hooks and hardware scars which will allow easy adaptation to advanced algorithms, and to develop complex software prototypes which fit into the ECLSS software architecture and will be shown in an ECLSS hardware testbed to increase the autonomy of the system. Covered here are the preliminary investigation and evaluation process, aimed at searching the ECLSS for candidate functions for automation and providing a software hooks and hardware scars analysis. This analysis shows changes needed in the baselined system for easy accommodation of knowledge-based or other complex implementations which, when integrated in flight or ground sustaining engineering architectures, will produce a more autonomous and fault tolerant Environmental Control and Life Support System.

Dewberry, Brandon S.↗

NASA NTRS2020

Characterization and Commissioning of a Ka-Band Ground Station for Cognitive Algorithm Development

In 2018, the Cognitive Communications and Propagation projects completed installation and checkout testing of a new Ka-Band ground station at the NASA Glenn Research Center in Cleveland, Ohio. The Cognitive Algorithms Demonstration Testbed (CADeT) was developed to provide a fully characterized and controllable dynamic link environment to researchers looking to demonstrate hardware and software aligned with atmospheric sensing and cognitive algorithms. CADeT integrates a host of precision control and measurement systems in addition to repurposing a 5.5 meter beam-waveguide dish platform previously used with the Advanced Communications Technology Satellite (ACTS). This paper will discuss the laboratory testing of ground station components with a emphasis on elements vital to achieving link budget requirements including characterization of the new Gallium Nitride (GaN) Solid State Power Amplifier (SSPA) and far-field measurements of the new antenna feed. Finally, the paper discusses in-situ tests conducted with CADeT and the Tracking and Data Relay Satellite System (TDRSS) to validate laboratory results and make necessary link budget adjustments before reviewing the lessons learned.

Cameron M Seidl↗

DOE OSTI2020

The JSNS 2 data acquisition system

The JSNS 2 (J-PARC Sterile Neutrino Search at J-PARC Spallation Neutron Source) experiment aims to search for neutrino oscillations over a 24 m short baseline at J-PARC. The JSNS 2 inner detector is filled with 17 tons of gadolinium(Gd)-loaded liquid scintillator (LS) with an additional 31 tons of unloaded LS in the intermediate γ-catcher and an optically separated outer veto volumes. A total of 120 10-inch photomultiplier tubes observe the scintillating optical photons and each analog waveform is stored with flash analog-to-digital converters. Here, we present details of the data acquisition, processing, and data quality monitoring system. We also present two different trigger logics which are developed for the beam and self-trigger.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

NASA NTRS1998

Evolvable Hardware for Spacecraft Autonomy

Evolvable hardware is a recently proposed technology in which reconfigurable hardware under the control of and evolutionary (genetic) algorithm can automatically self-reconfigure into sonfigurations with the desired behavior.

digital↗

NASA NTRS2022

Docking the Mars 2020 Perseverance Robotic Arm

The Mars 2020 Perseverance Rover includes an innovative Sample Caching Subsystem (SCS). Two key features of SCS are the ability to collect and process rock and regolith samples for possible future return to Earth and the ability to switch between different types of drill bits for coring rocks, abrading rocks, and collecting regolith. These capabilities are enabled by a Corer mounted on the end of a Robotic Arm and a Bit Carousel mounted on the front of the rover body. Beneath the Bit Carousel, a smaller Sample Handling Arm can insert and remove sample tubes from sampling bits in the carousel. For the Corer to interface with the Bit Carousel so that it can exchange drill bits and hand off rock samples, the Robotic Arm must maneuver the Corer to dock with the Bit Carousel. Docking serves two primary purposes: it precisely aligns the Corer with the hardware inside the Bit Carousel, and it applies enough preload between the Corer and the Bit Carousel to make them stay aligned through the process of bit exchange.The docking assembly consists of four concave alignment cones mounted on a large rotating ring, through the center of which the drill can exchange bits and samples with the Bit Carousel. The coring drill includes four alignment posts which mate with the four cones on the dock. Docking uses an algorithm we call “Force-Corrected Docking”, which means it iteratively reads the force/moments reported by the FTS, performs a small motion to reduce sideload and moments while increasing preload, and repeats until reaching a deadband around the target preload. Because docking is a critical function for SCS, the dock hardware and algorithm have been tested thousands of times over 7 years in various stages of development. The culmination of this work is a reliable docking system which has been demonstrated and used in flight.

Warner, Antonia↗

NASA NTRS2013

Robonaut 2 on the International Space Station: Status Update and Preparations for IVA Mobility

Robotics engineers, ground controllers and International Space Station (ISS) crew have been running successful experiments using Robonaut 2 (R2) on-board the ISS for more than a year. This humanoid upper body robot continues to expand its list of achievements and its capabilities to safely demonstrate maintenance and servicing tasks while working alongside human crewmembers. The next phase of the ISS R2 project will transition from a stationary Intra Vehicular Activity (IVA) upper body using a power/data umbilical, to an IVA mobile system with legs for repositioning, a battery backpack power supply, and wireless communications. These upgrades will enable the R2 team to evaluate hardware performance and to develop additional control algorithms and control verification techniques with R2 inside the ISS in preparation for the Extra Vehicular Activity (EVA) phase of R2 operations. As R2 becomes more capable in assisting with maintenance tasks, with minimal supervision, including repositioning itself to different work sites, the ISS crew will be burdened with fewer maintenance chores, leaving them more time to conduct other activities. R2's developers at the Johnson Space Center (JSC) are preparing the R2 IVA mobility hardware and software upgrades for delivery to the ISS in late 2013. This paper summarizes R2 ISS achievements to date, briefly describes the R2 IVA mobility upgrades, and discusses the R2 IVA mobility objectives and plans.

Ahlstrom, Thomas D.↗

DOE OSTI2024

Hls4ml Synthesis Testing

HLS4ml (high level synthesis for machine learning) Is a Python package used to translate commonly used open-source machine learning models into HLS. This is useful in machine learning applications on FPGAs. Machine learning algorithms are only as fast as the hardware that they are used on, and some applications require high speed without sacrificing accuracy. In these situations, an FPGA is a good choice since it is faster than a CPU or a GPU, but programming an FPGA is difficult. This is where HLS4ml can be used to simplify the process, as a well-known learning model can be converted to HLS and more easily deployed onto an FPGA. There are many use cases for a machine learning algorithm running on an FPGA. For example, detectors in a particle accelerator cannot keep every event that they detect, and so a computer must decide which events to keep and which to discard. Using an FPGA with a machine learning algorithm would be a good way to keep as many events as possible.

Swanson, Caiden↗

DOE OSTI2024

hls4ml

hls4ml (high level synthesis for machine learning) Is a Python package used to translate commonly used open-source machine learning models into HLS. This is useful in machine learning applications on FPGAs. Machine learning algorithms are only as fast as the hardware that they are used on, and some applications require high speed without sacrificing accuracy. In these situations, an FPGA is a good choice since it is faster than a CPU or a GPU, but programming an FPGA is difficult. This is where hls4ml can be used to simplify the process, as a well-known learning model can be converted to HLS and more easily deployed onto an FPGA. There are many use cases for a machine learning algorithm running on an FPGA. For example, detectors in a particle accelerator cannot keep every event that they detect, and so a computer must decide which events to keep and which to discard. Using an FPGA with a machine learning algorithm would be a good way to keep as many events as possible.

Swanson, Caiden↗

DOE OSTI2023

Enabling Scalable VQE Simulation on Leading HPC Systems

Large-scale simulations of quantum circuits pose significant challenges, especially in the context of quantum chemistry, due to the number of qubits, circuit depth, and the number of circuits needed per problem. High-performance computing (HPC) systems offer massive computational capabilities that could help overcome these obstacles. We developed a high-performance quantum circuit simulator, called NWQ-Sim, and demonstrate its capability to simulate large quantum chemistry problems on NERSC's Perlmutter supercomputer. Integrating NWQ-Sim with XACC, we have executed QPE and VQE algorithms for downfolded quantum chemistry systems at unprecedented scales. Our work demonstrates the potential of leveraging HPC resources to advance quantum chemistry and other applications of near-term quantum devices.

Wang, Meng↗

DOE OSTI2025

Even Higher-Level Synthesis: An Exploration of AI Hardware Accelerators using HLS4ML

With the rise of artificial intelligence, the popularization of deep learning, and a constantly evolving industry, the demand for flexible and efficient tools has never been greater. As algorithms grow more complex, their runtime and energy consumption increase exponentially. Customized hardware accelerators, long used for specific mathematical operations, remain essential for managing modern applications' computational and power demands. Hardware accelerators can speed up complex computations by orders of magnitude, but their manual design and verification processes are often challenging and time-consuming. High-Level Synthesis (HLS) provides a solution by transforming high-level algorithm descriptions, typically written in C++ or SystemC, into synthesizable RTL suitable for hardware implementation. This approach reduces development time for RTL engineers while offering flexibility beyond what traditional handwritten RTL can provide. We extended this capability to the machine-learning domain with the open-source framework hls4ml, which allows neural networks trained in Python frameworks like Tensorflow or PyTorch to be synthesized into efficient hardware representations for the traditional FPGA and ASIC flows. This breakthrough addresses the growing need for reduced design turnaround and easy verification of ML hardware accelerators with low latency and power efficiency constraints. During this tutorial, we will demonstrate how Python complements HLS by simplifying the ML design process, bridging the gap between software and hardware development. Attendees will explore how we translate neural networks modeled in Python into fixed-point C++ models suitable for HLS workflows. We will dive into strategies like Value-Range Analysis and Quantization-Aware Training, which optimize these designs for deployment and evaluate their accuracy, power consumption, and energy efficiency. To exemplify these concepts, experts from Fermilab will share their experiences applying this technology to high-energy physics experiments, where real-time, low-latency processing is critical. Over the years, Fermilab engineers have demonstrated how deep neural networks, optimized for hardware using hls4ml, can meet the stringent requirements of trigger systems at the CERN Large Hadron Collider. These systems rely on rapid decision-making to process immense data volumes while retaining only the most relevant events for further analysis. The application of hls4ml has also been extended to innovative technologies like smart pixel arrays. These smart pixels integrate ML inference capabilities directly into sensor devices, enabling localized data processing at the pixel level. This approach drastically reduces the need to transmit raw data to external processing units, significantly decreasing power consumption and latency. By embedding neural networks within the pixel architecture, the smart pixels can identify and prioritize relevant data in real time, providing a highly efficient solution for edge computing in scenarios such as particle detectors and imaging systems. Fermilab's work highlights the potential of hardware-accelerated ML in scenarios where both speed and power efficiency are mission-critical. Through this tutorial, attendees will gain valuable insights into the challenges and solutions of deploying ML in hardware. Understanding how HLS and hls4ml streamline the development of neural network-based hardware accelerators is fundamental for the industry's future. Participants will learn how these technologies are shaping the future of AI and scientific computing.

Di Guglielmo, Giuseppe [Fermilab]↗